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Papers

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Listing all the work. Click on the title of the paper to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

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on topic: All topicsADC design problems Cellular automata Design of System-on-chip (SoC) and IP-blocks Design of VLSI elements Design of VLSI signal processors Design of analog and mixed functional blocks of VLSI Design of digital functional blocks of VLSI Design of fault-tolerance systems Design of micro-electromechanical systems Design of nanoelectronic devices Design of nanoelectronic devices based on Josephson junctions Design of photodetecting VLSI Design of radiation-resistant VLSI Design of technological processes Designing components for aerospace and navigation technology Genetic algorithms in VLSI CAD Methods and algorithms for automated layout design Methods for high-level simulation Methods of device technology simulation of VLSI Methods of digital information processing and digital filters Methods of electro-thermal simulation Methods of logic synthesis and functional logic simulation ... Methods of simulation of VLSI electrical characteristics Models of devices for circuit simulation Neural networks Problems of development of sensory microcircuitry Simulation of data transfer channels Study of the magnetic properties of materials Unconventional computing systems Web-based VLSI CAD design of memory cells

Selected papers: year 2014

In selection - 150 papers

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A
	A 8-bit flash ADC with reduced DNL Accuracy and adequacy of the analytical modeling of the temperature distribution in thermal microsystems An 8-bit segmented DAC with high conversion rate Analysis and synthesis of arithmetic unit of a field of Galois of prof. Pospelov D.A. An approach to hardware test point insertion automation based on hardware reengineering tools Ant algorithm for determining the critical linkages in VLSI Application of grid representations for compression of graphical information Application of spectrum sensing technique for the design of radio receivers of spectrally sparse signals Application of the principles of adaptive filtering signals to the synthesis of invariant control systems unknown dynamic plants A stick-diagram based standard cell layout synthesis tool A technique to the design-for-testability automation of analogue IC based on OBIST Automated design of Networks-on-Chip with custom topology
B
	Bioinspired VLSI chip planning methods Biquad digital filters with non-canonical z-plane topography of poles
C
	Calibration of numerical TCAD model for 180 nm SOI MOSFETs Clock Tree Synthesis Optimization Communication fabric IP-core for a system-on-chip Comparative analysis of different hardware decoder architectures for IEEE 802.11ad LDPC code Comparative analysis of efficiency of different variants of the dynamic programming method for solving the problem of optimal placing of elements on the chip Counterfeit IC detection based on s-parameters measurements
D
	Decomposition Algorithm of the Electronic Circuits with Elements with Varied Area Decomposition and Minimization of Binary Decision Diagrams for Systems of Specified Boolean Functions Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors Dependence of MCU Sensitivity in SRAM on Data Pattern and angle of incident Design Principles and Numerical Simulation of Microthermomechanical IR Imagers with Optical Readout Design of IC package with ceramic substrate for multicore processor Design of basic blocks for millimeter wave receiver in CMOS 90 nm Design of technology process of silicon-germanium heterobipolar transistors manufacture Design of the error-correcting code blocks using the two-phase CMOS logic elements Development and modeling for submicron PDCFET transistors Development monolitic integrated SiGe HBT reciver for 57-64 GHz application Development of methods for the analysis of defects in the gate dielectric on the test structures in the wafers Development of the simulation environment of inertial navigation systems Device for calculation of vector dot product with error correction based on residue number system
E
	Electrostatic protection of BiCMOS IC's Estimation of digital sensor's influence on the management systems efficiency Evolution in the area of multicore heterogeneous video data processing systems Experimental Verification of Some Laser Techniques' Approximations
F
	FPGA prototyping for functional verification of multi-core processors FPGA reverse engineering by model-driven development Femtosecond Laser System for VLSI Heavy Ion Induced Single Event Effects Hardness Testing Finite state machine state splitting for power minimization Flip-flops and Drivers for High-Speed Current-Steering CMOS DACs Formulation of the stability criterion of the third order IIR digital filters in the space of coefficients of the denominator of transfer function
G
	Gate nets routing in nanometer standard cells with ports placement
H
	Hardware acceleration of digital simulation Hardware implementation of FIR filter based on number-theoretic fast Fourier transform in residue number system High-speed content addressable memory block design
I
	IP-Core "ACC_Cores" as part system-on-chip. Multifunctional hardware accelerator Fast Fourier Transform - FFT_RT_Core Image compression by using tensor approximation Implementation of the combustion problem main functions based on specialized vector coprocessor FMA operations Influence of CMOS Hall Effect Sensor Layout on its Magnetic Sensitivity Infrared focal plane arrays (FPA) with thermopile thermal radiation MEMS sensors Initial placement of digital logic cells in integrated circuits considering net priority Integrated Step Up/Down Power Converter With Dynamic Control Of Clock Frequency Interconnect Verification Methods Based on Unified Test Infrastructure Inverter-based pseudo-flash ADC with low power consumption Investigation of the possibilities of practical application of the adiabatic logic to reduce power consumption of VLSI
K
	Key features of static timing analysis and SDC development for complex system-on-chip ASIC with multiple asynchronous clock domains
L
	LMS adaptive filtering algorithm: first or unique one for practical applications? Linear synthesis - a new approach to the logical design of k-valued digital structures
M
	Mathematical model for complex digital circuits and microsystems projects debugging based on presenting the latest as a family of stationary dynamical systems Membrane-based thermal flow sensor working on calorimetric principle Method of mathematical testing of programs for transient analysis in EDA packages Method of placement blocks of three dimensional integration IC Methodology of the optimization and efficiency evaluation for the Secondary Cache Methods of designing custom IP-blocks based on the elements with regular topological structure in layers of polysilicon and diffusion Methods of determination the coefficients of quasi-optimal FIR-filter for convolution of pseudorandom binary sequence Methods of high-frequency correction for analog sections in ultrafast ADCs with differential input Methods of implementation of high-speed serial channels CMOS transceivers on a physical level Methods of regulation of computation in parallel dataflow computating system Minimization of undesired layout patterns during standard cell synthesis Model Order Reduction Techniques with Preservation of Sparseness in Circuit Simulation Modeling TID leakage current in MOS-structures under x-ray and gamma irradiation Modeling memristor circuits Modeling of plasma-chemical etching technology in CF4/H2 mixture Modernized design methodology blocks complex software and hardware systems with regard to their reliability parameters Modern methods of functional verification RTL-models blocks for VLSI microprocessor Motion Estimation IP-core Implementation for H.264 Full HD Video Codec
N
	NAND Flash memory controller IP-core Nonlinear Phase Macromodel for the Analysis of oscillator circuits Numerical model for MISFETs characterization
O
	On one method of defining functional coverage metrics for microprocessor testing Optimization of instrumentation amplifiers structures with indirect current feedback instrumentation amplifiers
P
	Parallel VLSI Layout Decomposition Algorithm for Double Patterning Possibilities of The distributed subsystem topological design, built on the basis of client-server technologies Powering the Directed VLSI Firmware and Software Testing with Data Flow Aware Limited Branch Alternation Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions Processing speed increase and hardware cost reduction in Hsiao decoders Proton and gamma-radiation ionizing effect comparative results Prototyping linux kernel drivers in userspace with lua scripting language Pseudo-differential cascode output buffer for high-speed serial data transmission across a channel with high losses
Q
	Quasi optimal in time algorithm of designing of analog circuits
R
	Radiation-hardned CMOS VLSI SRAM in bulk technology Rank codec IP-core Readout circuit from the nonvolatile memory Recent software for VLSI operating in space radiation environment estimation analysis Recognition and interpretation of erroneous behavior in simulation-based hardware verification Research and development of structures for the extraction of circuit model parameters accounting dose radiation effects in submicron VLSI Research of fully CMOS compatible EEPROM cell Research the principles of operation of the input block for the parallel dataflow computing system Reusable complex Soc level tests creating and debugging method
S
	SEE sensitivity changes at different TID levels SOI MOSFET Compact SPICE model for radiation-hardened 0.35 µm IC design Sampling theorem applied to data interpolation problem Scalable diode macromodel with high modeling accuracy Shortest trees construction on the basis alternatives field crystallization method Sigma-delta ADC for capacitive accelerometer Simulation modeling for survivability evaluation of digital control systems Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection Singularity of radiation-hardened amplifiers circuitry based on BiMOS ABMC Spaceborne SAR spatial resolution and radiometric characteristic determination using a method of echo signal digital simulation Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects Spread spectrum clock generator design methods Static and Dynamic Error of Current-Steering DACs Statistical approach to multiple cell upsets description in highly scaled memory circuits Structural optimization and development of the monolithic IC SiGe active attenuator Structure of control vector by optimization of analog circuits Synthesis of memory units using a description of design rules via Boolean functions of layout objects System Debugging Tools for Recurrent Computing Device System approach to design UHF RFID reader transceiver ICs System for parallel processing of mobile operator traffic
T
	Testing and limiting metrological possibilities of pulse-potential ADC in SoC The DICE cells layout design for the hardened CMOS 28 nm SRAM The Numerical Algorithm for Stability Analysis of Large Dynamical Systems The architecture of scheduler of mapping processor of PDCS "Buran" The capabilities of usage virtual platforms for verification of RTL-models of complex co-processor blocks The main parameters and equations of basic configurations multidifferential operational amplifiers with high impedance node The method for photosensitive matrix VLSI modulation transfer function simulation The method of EFSM extraction from HDL: application to functional verification The method of harmonic balance for electrothermal analysis of periodic steady states of IC The method of peak current estimation at logic level taking into account simultaneous switching of inputs The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control The principle of factorization in a problem of design of RBS-based processors The technique of test generator realization for built-in self-test circuitries The two-phase 28-nm CMOS inverters in SET-tolerant logics Transistor placement at standard cell level Two current mirrors - twice bandgap
U
	UWB Balun-LNA Unified approach to radiation hardness assurance of high-speed ASICs Universal scan based JTAG compatible VLSI debug structure Using of VBIC model for SiGe integrated circuit application Using the gate capacitance of MOS transistor as LPF's capacitance and its impact on the PLL's characteristics of quality
V
	VLSI microprocessor monitoring unit Variable-length code packing IP-core Verification of Logical Descriptions of Combinational Circuits Verification of divers systems based on integrated circuits Voltage References on FET Differential Pairs with control pn-transition
W
	Wideband Multichannel 60 GHz Switches in 90 nm CMOS Process