| FPGA reverse engineering by model-driven development |
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| Authors |
| | Cheremisinov D.I. |
| Date of publication |
| | 2014 |
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| Abstract |
| | The problem of converting of the digital system realized on FPGA Spartan 3, into VHDL-descriptions suitable for synthesis of ASIC is considered. The program for the decision of this problem is constructed as the automation tools of the model-driven development. |
| Keywords |
| | FPGA, ASIC, reverse engineering, graph rewriting and transformations. |
| Library reference |
| | Cheremisinov D.I. FPGA reverse engineering by model-driven development // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 1. P. 25-30. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D062.pdf |
