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Inverter-based pseudo-flash ADC with low power consumption
Authors
	Morozov D.V.
	Pilipko M.M.
	Piatak I.M.
Date of publication
	2014
Abstract
	An inverter-based pseudo-flash ADC is presented. CMOS inverters are used instead of a reference ladder of well matched resistors and comparators to reduce power consumption of the ADC. Influence of temperature and technology process variations on the inverters threshold voltages is considered. The ADC occupies 60120 um2 on the chip. The results of ADC chip measurements in UMC 180 nm CMOS technology showed that sampling rate is 100MSps, power consumption is 1,9 mW. Maximal DNL/INL are 0.6 LSB and 0.9 LSB respectively, the FOM is 0.63 pJ.
Keywords
	flash ADC, CMOS inverter, priority encoder, power consumption
Library reference
	Morozov D.V., Pilipko M.M., Piatak I.M. Inverter-based pseudo-flash ADC with low power consumption // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 25-28.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D064.pdf