| Verification of Logical Descriptions of Combinational Circuits |
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| Authors |
| | Cheremisinova L.D. |
| Date of publication |
| | 2014 |
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| Abstract |
| | Methods and their program implementations are described which are intended for verification of logical descriptions of combinational circuits under design and allow to detect errors at early design stages. Two approaches to solution of the verification problem are implemented: ones based on simulation of a combinational circuit and others based on formulating the verification problem as conjunctive normal form satisfiability checking |
| Keywords |
| | design automation, verification, simulation, satisfiability of conjunctive normal forms |
| Library reference |
| | Cheremisinova L.D. Verification of Logical Descriptions of Combinational Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 1. P. 9-14. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D035.pdf |
