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Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions
Authors
	Bezglasnaya K.A.
	Kolbasov Y.S.
	Medvedev I.A.
	Putrya F.M.
Date of publication
	2014
Abstract
	Design flow for System on Chip assumes creation of local test environments for IP cores and test environments for System on Chip model which imitates scenarios according to its application. Depends on the number of IP cores and IP cores complexity in System on Chip, time for development of verification infrastructure are increasing and become comparable with time for development and debugging of test scenarios. The article focuses on problems of labor costs which is required for creation of verification infrastructure and their solutions. The main approaches for solutions of this problems are unification of verification components and automation for verification infrastructure creation.
Keywords
	verification, System on Chip, UVM, unification, reusing, test environment, automation.
Library reference
	Bezglasnaya K.A., Kolbasov Y.S., Medvedev I.A., Putrya F.M. Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 69-74.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D118.pdf