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Key features of static timing analysis and SDC development for complex system-on-chip ASIC with multiple asynchronous clock domains
Authors
	Dergachev P.N.
	Filimonova I.P.
	Shevchenko P.A.
Date of publication
	2014
Abstract
	Modern ASICs is difficult, complex systems consisting of a large number of IP blocks from different vendors . The main task of the developer of such systems - ensuring the achievement of the set of system parameters. Correctness of STA (Static Timing Analysis) is defined by correct construction of SDC (Synopsys Design Constraints) file. In the case of developing an integrated project that uses a plurality of asynchronous clock domains , the development and testing of the SDC file - engineering challenge. The article provides the method for constructing and testing procedure and debugging SDC file for DTSP (digital television signals processing) VLSI.
Keywords
	STA (static timing analysis), SDC (synopsys design constraints), verification, system-on-chip, DTSP VLSI (digital television signal processing VLSI), IP block, design flow.
Library reference
	Dergachev P.N., Filimonova I.P., Shevchenko P.A. Key features of static timing analysis and SDC development for complex system-on-chip ASIC with multiple asynchronous clock domains // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 75-80.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D115.pdf