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| Authors |
| | Sysoev I.Y. |
| | Gabidulin E.M. |
| Date of publication |
| | 2014 |
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| Abstract |
| | This paper presents a hardware implementation of the codec for rank codes. Parameters of rank code are (8,4,5). Algorithm was implemented on FPGAs Spartan-3AN and Spartan-6. The codec operates with elements from Galois field GF (2^8). The device can process informational data stream up to 77 MiB/s. Proposed results should help understanding rank code structure and simplify the problem of its application. |
| Keywords |
| | encoding, decoding, fast calculations, IP-core, rank codes, Euclidian Algorithm |
| Library reference |
| | Sysoev I.Y., Gabidulin E.M. Rank codec IP-core // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 61-66. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D172.pdf |
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