| Design of the error-correcting code blocks using the two-phase CMOS logic elements |
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| Authors |
| | Katunin Yu.V. |
| | Levin K.E. |
| Date of publication |
| | 2014 |
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| Abstract |
| | It’s possible to use two-phase CMOS logic elements to improve SET-tolerance of the error-correction code blocks. Simulation results of two-phase 28 nm CMOS XOR elements with various configurations of internal electrical couplings under influence of the input voltage noise pulses are presented. Test library contained two-phase logic elements was designed. Using this library layout of the Hsiao (72, 64) error-correcting code block was synthesized. |
| Keywords |
| | Error-correcting code, two-phase CMOS logic, layout synthesis |
| Library reference |
| | Katunin Yu.V., Levin K.E. Design of the error-correcting code blocks using the two-phase CMOS logic elements // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 33-36. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D071.pdf |
