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Interconnect Verification Methods Based on Unified Test Infrastructure
Authors
	Medvedev I.A.
	Putrya F.M.
Date of publication
	2014
Abstract
	Interconnect verification in a modern Systems-on-Chip (SoC) is important part of design. Offered in the paper ways of test inputs generation, mechanisms of function model design and set of metrics for productivity analysis solve specific tasks of communication logic verification with complex topology, multiple interfaces and bridges between communication layers. Test infrastructure unification increase verification efficient with suggestion of interconnect development and increasing of it ammount.
Keywords
	interconnect, system-on-chip, network-on-chip, verification, UVM, TLM, SystemC
Library reference
	Medvedev I.A., Putrya F.M. Interconnect Verification Methods Based on Unified Test Infrastructure // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 85-90.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D092.pdf