| Processing speed increase and hardware cost reduction in Hsiao decoders |
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| Authors |
| | Petrov K.A. |
| Date of publication |
| | 2014 |
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| Abstract |
| | Circuit analysis of elements widely applied in random acces memory was carried out. A set of simplified elements for the decoder is suggested. Application of the introduced decoders will allow processing speed increase by 13-26% and hardware cost reduction by 21-34% by means of simplified elements application and reduction of number of connections between them. |
| Keywords |
| | error correction coding, circuit technique of coder-decoder, Hsiao code, RAM |
| Library reference |
| | Petrov K.A. Processing speed increase and hardware cost reduction in Hsiao decoders // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 37-40. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D107.pdf |
