Reusable complex Soc level tests creating and debugging method

Golovina, E.; Makeeva, M.; Nikolaev, A.V.; Putrya, F.M.; Smirnov, A.A.

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Authors

Date of publication

2014

Abstract

System-on-chip (SoC ) - are complex devices consisting of multiple IP-Cores interconnected whith each other. Even in case of integration into SoC of fully veryfied IP-Core (for example, by using the UVM methodology), a high probability of errors occurring during interaction of IP-Core with other elements of the system or in case of parallel operation of other IP-Cores and processes. High load on all nodes in the system may affect the actual IP-core functional parameters. To detect these problems at the SoC design stage it is necessary to create the set of complex tests, providing various types of loads on SoC under verification nodes. Algorithms and program code of such tests are strongly attached to the structure and architecture of SoC, it is difficult to develop and debug such tests. This often leads to the inability to properly test SoC model in the allotted time. In this paper we propose a creating and debugging complex tests method, wich simplifyes their development and reuse at all stages of SoC design and between projects.

Keywords

Soc, Verification, complex tests, system level tests, integration tests, object oriented programming

Library reference

Golovina E., Makeeva M., Nikolaev A.V., Putrya F.M., Smirnov A.A. Reusable complex Soc level tests creating and debugging method // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 2. P. 45-50.

URL of paper

http://www.mes-conference.ru/data/year2014/pdf/D026.pdf