Listing of all the works of the organization. Click on the work title to get the full information.
| 2005 | |
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Gourary M.M., Rusakov S.G., Ulyanov S.L., Zharov M.M., Mulvaney B.J.
Adaptive method of harmonic balance
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Skrylev P.A., Smoleva O.S.
Architecture of the unified computing block for contactless photon system of measurement of parameters of a rail track
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Egorov Yu.B., Lyalinsky A.A.
Automation of synthesis of VHDL-AMS models for the mixed and analog behavioural simulation
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Solovyev R.A., Gavrilov S.V.
Delay noise analysis, using graph of constraint pairs
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Bobkov S.G., Tokarev V.E.
Designing of custom-made blocks taking into account extraction RC parasitic parameters
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Rakitin V.V., Uvarov A.K.
Development of integral digital filters for sigma-delta converters using MATLAB
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Djigan V.I.
Efficiency of adaptive signal processing algorithms implementation on basis of MULTICORE SoC
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Kornilov A.I., Semenov M.Y., Lastochkin O.V., Kalashnikov V.S.
Methodology of designing of specialized calculators on the basis of the automated generation of technologically independent IP-blocks
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Bezrukov A.E., Rusakov A.S., Tkachev D.F., Khapaev M.M.
Methods of the parasitic extraction of interconnect in the integral circuits
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Gavrilov S.V., Glebov A.L.
Noise analysis of digital circuits with accounting of logic constraints
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Pugachev A.A.
Numerical Simulation of Photosensitive VLSI Pixels
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Kornilov A.I., Semenov M.Y., Lastochkin O.V., Kalashnikov V.S.
Principles of construction of specialized calculators based on residual arithmetics
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Bobkov S.G.
Problems of creation of computers of series "Baguet" for problems with increased requirements to reliability of long-term functioning
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Arakelov A.A., Sidorov E.A., Bobkov S.G.
SRAM memory controller to maximize switch performance
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Bobkov S.G., Evlampiev B.E., Sidorov A.Yu.
The block of self-testing of internal memory
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| 2006 | |
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Aryashev S.I., Bobkov S.G., Zubkovskiy P.S.
64-bit superscalar embedded RISC microprocessor
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Gavrilov S.V., Glebov A.L., Lyalinskaya O.V., Solovyev R.A.
Application of standard cell characterization results in statistical timing analysis
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Prokopenko N.N., Budyakov A.S., Kryukov S.V.
Architecture and circuit design of precision differential amplifiers with high common mode rejection ratio
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Prokopenko N.N., Budyakov A.S., Sergeenko A.I.
Buffer stage of operational amplifiers with low output impedance and option rail-to-rail
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Prokopenko N.N., Budyakov A.S., Kovbasyuk N.V.
Circuit design methods of increasing the reliability of operational amplifiers with maximum speed in high-signal mode
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Krutchinsky S.G., Prokopenko N.N., Starchenko E.I.
Compensation of parasitic capacitances of the active elements in electronic devices
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Stempkovsky A.L., Kornilov A.I., Semenov M.Y., Lastochkin O.V., Kalashnikov V.S.
Construction of systems of raised reliability based on residual arithmetics with application of modern methods and tools of designing
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Budyakov A.S., Prokopenko N.N., Starchenko E.I., Savchenko Ye.M., Krutchinsky S.G.
Experience in design and modeling of analog circuits with limited parameters based on Russian bipolar technology
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Kharlamov S.A.
Information problems of supervision and control in a micromechanical gyroscope system
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Djigan V.I.
Lattice adaptive filtering algorithms is a new component of applied library for “Multicore” VLSI signal controller
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Prokopenko N.N., Budyakov A.S., Kovbasyuk N.V., Krutchinsky S.G., Savchenko Ye.M.
Methods of compensation of basic components of the output capacitance of transistors in analog chips
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Egorov Yu.B., Rusakov S.G., Lyalinsky A.A.
Modelling of radio engineering circuits with digital modulation within the frames of VHDL-AMS simulation systems
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Djigan V.I.
Modern adaptive signal processing: problems and solutions
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Bojko A.Ya., Bezrukov A.E., Rusakov A.S., Tkachev D.F., Khapaev M.M.
New Algorithm for the 2D Capacitance calculation in the interconnect parasitic extraction problem
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Pugachev A.A., Osochkin S.S.
Physical-topological model of modulation transfer fuction
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Dvornikov O.V., Tchekhovski V.A., Krutchinsky S.G., Shchekin D.A., Shcherbinin I.P., Prokopenko N.N., Starchenko E.I.
Practical developments and projects for substitution of import and IP-projects on base of radiation-resistant analog array chip
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Solovyev R.A., Glebov A.L., Gavrilov S.V.
Static timing analysis aware false conduct path detection in terms of logic implication
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Adamov Yu.F., Gorshkova N.M., Krupkina T.Yu.
The Utilization of Photolayers for Bipolar Transistors Implementation in Typical CMOS Process
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Prokopenko N.N., Budyakov A.S., Savchenko Ye.M., Korneev S.V.
The dynamic extreme parameters of operational amplifiers with voltage feedback and amplifiers with current feedback in linear and nonlinear modes
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Gourary M.M., Ulyanov S.L., Mulvaney B.J.
The simulation method of nonlinear distortion of radio frequency circuits with digital modulation in circuit simulators
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Zharov M.M., Rusakov S.G.
Two-level reduction of models of parasitic circuits of the high order
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| 2008 | |
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Uvarov A.K., Rakitin V.V.
16-digit 6.4 MHz CMOS sigma-delta ADC for sound processing
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Rusakov A.S., Khapaev M.M.
Accuracy Improvement of the Interconnect Parasitic Capacitance Extraction
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Djigan V.I.
Adaptive arrays for digital communication systems: problems and solutions
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Djigan V.I.
Algorithms for adaptive filtering of nonstationary signal based on parallel computations
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Kryukov S.V., Prokopenko N.N., Konev D.N.
Architecture of differential operational amplifiers with increased common-mode noise stability
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Budyakov A.S., Prokopenko N.N., Schmalz Klaus, Scheytt Christoph, Ostrovskyy P
Circuit design of UHF operational amplifiers for analog interfaces with strong negative feedback
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Gorshkova N.M.
Constructive and technological design of silicon color photocells with deep color separation based on isotype ð+-ð junctions
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Muhanyuk N.N.
Development of technologically independent method of designing analog IC on the basis of library of parametrical cells
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Prokopenko N.N., Kryukov S.V., Khorunzhij A.V.
Features of the design of analog circuits using transistors with low Early voltage
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Bragin K.R., Gavrilov S.V., Kagramanyan E.R.
Logic-timing analysis methodology for characterization of custom blocks of digital CMOS IC
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Gudkova O.N., Gavrilov S.V.
Logical timing analysis of digital IC reliability with NBTI and HCI degradation effects
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Gourary M.M., Zharov M.M., Rusakov S.G., Ulyanov S.L.
Method of small-signal analysis for the simulation of multitone radio frequency circuits
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Prokopenko N.N., Budyakov A.S., Khorunzhij A.V.
Nonlinear modes in multidifferential operational amplifiers
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Prokopenko N.N., Budyakov A.S., Savchenko Ye.M.
Operational amplifiers with generalized current feedback
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Gourary M.M., Zharov M.M., Rusakov S.G., Ulyanov S.L.
Perturbation methods and selective methods in problems of a reduction of high-dimension models
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Pugachev A.A., Maklakova O.V., Kushnir A.A.
Photosensitive CCD VLSI TCAD modeling
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Kharitonov I.A., Petrosyants K.O., Orekhov E.V., Yatmanov A.P., Sambursky L.M.
Process and device simulation of CMOS SOI VLSI elements with an account for radiation effects
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Stenin V.Ya., Betelin V.B., Bobkov S.G., Krasnyuk A.A., Osipenko P.N., Cherkasov I.G., Chumakov A.I., Yanenko A.V.
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
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Stepchenkov Yu.A., Diachenko Yu.G., Bobkov S.G.
Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
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Kagramanyan E.R., Gavrilov S.V., Egorov Yu.B.
Standard cell characterezition methodoligy with respect MOSFET threshold voltage variation
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Solovyev R.A., Gavrilov S.V., Glebov A.L.
Statistical timing analysis aware of reconvergence of conduction paths and transition variations
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Amerbaev V.M., Telpukhov D.V., Konstantinov A.V.
The Bivalent Defect of Modular Codes. The Choise of Technological Modules, that Reduce Bivalent Defect
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Andreev P.P., Pugachev A.A., Khodosh L.S.
The project of the on-chip processor for videostream processing are developed. This project are based on Russian SIMD processor PARS
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| 2010 | |
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Polevikov V.V.
“Cycle-To-Cycle” methodology for timing analysis of high speed synchronous interfaces
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Rakitin V.V.
A Pipelined Analog-to Digital Converters With Digital Calibration
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Gourary M.M., Zharov M.M., Rusakov S.G., Lyalinsky A.A.
Application of Selective Techniques for Parametric Model Order Reduction
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Prokopenko N.N., Budyakov P.S., Serebryakov A.I.
Architecture of the microwave differential operating amplifiers with paraphase output
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Pugachev A.A., Stempkovsky A.L.
CMOS-APS element with high charge-collection efficiency
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Makarov A.B.
CMOS analog blocks technology migration
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Gourary M.M., Zharov M.M., Ulyanov S.L.
Computational method for determining phase noise in oscillators
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Adamov Yu.F.
Designing and production problems of smart sensors controllers
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Telpukhov D.V., Amerbaev V.M., Balaka E.S., Konstantinov A.V.
Design method of DSP-oriented modular logarithmic forward converter
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Sibagatullin A.G.
Influence Reduction of Technological Variations and Interferences on Signal Distortion in High-Speed Integrated ADC for System-on-Chip
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Prokopenko N.N., Serebryakov A.I., Budyakov P.S.
Method of Improving the Stability of Zero Analog Circuits with High-Impedance Node in the Conditions of Temperature and Radiation Effects
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Balaka E.S., Amerbaev V.M., Konstantinov A.V., Telpukhov D.V.
Methods of Scalar Products Speed Enhancement in Residue Logarithmic Number System Basis
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Djigan V.I.
Multichannel adaptive lattice filters
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Rusakov A.S., Romano V.
Numerical model of semiconductors with crystal heating
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Prokopenko N.N., Budyakov A.S., Schmalz Klaus, Scheytt Christoph
RF IP-blocks based on Fully differential OpAmps for Communication Systems
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Somov O.A., Adamov Yu.F., Gorshkova N.M., Sibagatullin A.G.
Reconfigurable Smart Sensor Controllers
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Amerbaev V.M., Kornilov A.I., Stempkovsky A.L.
Residue Logarithmic Number System – A New Possibilities for Residue Processors and Converters Designing
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Levchenko N.N., Okunev A.S.
Specialized the architecture of the parallel multicore dataflow computing system for solution of task FFT
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Makarov A.B., Kochkin I.P.
Technology migration of CMOS band gap voltage reference
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Gourary M.M., Rusakov S.G., Ulyanov S.L.
The Development of the Method for Analyzing Mutual Synchronization Mode of Oscillators in Integrated Circuits
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Gudkova O.N., Gavrilov S.V., Egorov Yu.B.
The Method of Section Approximation for Grid Optimization for Standard Cell Library Characterization
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Gudkova O.N., Skachkova E.P., Muhanyuk N.N., Gavrilov S.V., Solovyev R.A.
The Methods of Fast Characterization of Large Scale Integration Parameterized IP-blocks
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Sibagatullin A.G., Adamov Yu.F., Gorshkova N.M., Somov O.A.
The controller of the laser smoke fire detector with frequency filtering
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| 2012 | |
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Djigan V.I.
Adaptive Antenna Array in Real-Valued Arithmetic
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Prokopenko N.N., Budyakov P.S., Serebryakov A.I.
Autonomous parameters of of transistors of uncommited logic array ABMK_1_3 in radiation and temperature influences
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Gavrilov S.V., Gudkova O.N., Severtsev V.N.
CMOS circuit interval static timing analysis accounting for logic correlations
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Makarov A.B.
CMOS frequency divider by 2 with high stability of output signal duty cycle
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Budyakov P.S., Budyakov A.S., Prokopenko N.N.
Comparative analysis of active mm-wave SiGe mixers
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Andreev A.E., Pavisic I., Rusakov A.S.
Global placement algorithm for structured ASIC
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Soloviev A.N.
Gyro-free inertial navigation system
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Djigan V.I.
History, Theory and Practice of Adaptive Signal Processing
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Amerbaev V.M., Telpukhov D.V., Balaka E.S., Konstantinov A.V.
Implementation of Residue Number Systems Converter Combined with the Rounding Operation for DSP Applications
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Petrosyants K.O., Kharitonov I.A., Orekhov E.V., Sambursky L.M., Yatmanov A.P., Voevodin A.V.
Investigation of single event upset reliability for SOI CMOS SRAM cells using mixed-mode 3D TCAD-SPICE simulation
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Prokopenko N.N., Budyakov P.S., Pakhomov I.V.
Methods to improve the gain of the classical stages on bipolar transistors at low supply voltage
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Rakitin V.V.
Nanometer merged MOS devices modeling
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Amerbaev V.M., Stempkovsky A.L., Solovyev R.A.
Parallel computing in the ring of Gaussian integers over the Galois field GF(p)
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Levchenko N.N., Okunev A.S., Yakhontov D.E.
Study of mapping processor for dataflow parallel computing system "Buran"
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Kostukov E.V., Pospelova M.A., Pugachev A.A.
TCAD-model of CCD image sensor with vertical antiblooming
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Gavrilov S.V., Gudkova O.N., Pirutina G.A.
The Gate Delay Analysis Method Accounting for Simultaneous Input Switching
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Amerbaev V.M., Balaka E.S., Konstantinov A.V., Telpukhov D.V.
The RLNS Implementation for matrix algebra special problems solution
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Gourary M.M., Zharov M.M., Ulyanov S.L., Khodosh L.S.
The computational method for nonlinear distortion analysis with multitone test signals
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Gourary M.M., Zharov M.M., Rusakov S.G., Ulyanov S.L.
The modeling of NBTI effect in analog integrated circuits
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Adamov Yu.F., Balaka E.S., Gorshkova N.M., Sibagatullin A.G.
The power effective communication line for systems on a crystal with dynamic management of frequency synchronization
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Gourary M.M., Zharov M.M., Rusakov S.G.
The reduction algorithms of linear networks with inductances on the base of selective methods of elimination
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Levchenko N.N., Okunev A.S., Stempkovsky A.L.
The usage of dataflow computing model and architecture realizing these for exaflops performance system
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Levchenko N.N., Okunev A.S., Yakhontov D.E., Shurchkov I.O.
Variants of realization of controller for parallel dataflow computing system to work with vector and multioperand nodes
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Lyalinsky A.A.
Web-based Generation of Highlevel Models of Digital Cells
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Lyalinsky A.A.
Web-based automatic generation of input patterns at characterization of digital cells
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| 2014 | |
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Amerbaev V.M., Balaka E.S., Solovyev R.A., Telpukhov D.V.
Analysis and synthesis of arithmetic unit of a field of Galois of prof. Pospelov D.A.
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Rusakov A.S., Sheblaev M.V.
Decomposition Algorithm of the Electronic Circuits with Elements with Varied Area
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Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V.
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
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Soloviev A.N., Sablin A.V., Lyalinsky A.A.
Development of the simulation environment of inertial navigation systems
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Solovyev R.A., Balaka E.S., Telpukhov D.V.
Device for calculation of vector dot product with error correction based on residue number system
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Chaplygin Yu.A., Timoshenkov V.P., Shevyakov V.I., Adamov Yu.F.
Electrostatic protection of BiCMOS IC's
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Telpukhov D.V., Amerbaev V.M., Balaka E.S., Solovyev R.A.
Hardware implementation of FIR filter based on number-theoretic fast Fourier transform in residue number system
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Aryashev S.I., Barskikh M.E., Bobkov S.G., Zubkovskiy P.S., Ivasyuk E.V.
Implementation of the combustion problem main functions based on specialized vector coprocessor FMA operations
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| | |
Djigan V.I.
LMS adaptive filtering algorithm: first or unique one for practical applications?
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Prokopenko N.N., Chernov N.I., Yugai V.Ya.
Linear synthesis - a new approach to the logical design of k-valued digital structures
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Ivannikov A.D., Stempkovsky A.L.
Mathematical model for complex digital circuits and microsystems projects debugging based on presenting the latest as a family of stationary dynamical systems
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Aryashev S.I., Bobkov S.G., Sayapin P.V.
Methodology of the optimization and efficiency evaluation for the Secondary Cache
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Gavrilov S.V., Ivanova G.A., Manukyan A.A.
Methods of designing custom IP-blocks based on the elements with regular topological structure in layers of polysilicon and diffusion
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Prokopenko N.N., Serebryakov A.I., Butyrlagin N.V.
Methods of high-frequency correction for analog sections in ultrafast ADCs with differential input
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Klimov A.V., Zmejev D.N., Levchenko N.N., Okunev A.S.
Methods of regulation of computation in parallel dataflow computating system
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Zharov M.M., Rusakov S.G.
Model Order Reduction Techniques with Preservation of Sparseness in Circuit Simulation
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Rakitin V.V.
Modeling memristor circuits
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Gourary M.M., Rusakov S.G., Ulyanov S.L.
Nonlinear Phase Macromodel for the Analysis of oscillator circuits
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Zmejev D.N., Levchenko N.N., Okunev A.S., Stempkovsky A.L.
Research the principles of operation of the input block for the parallel dataflow computing system
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Zharov M.M.
The Numerical Algorithm for Stability Analysis of Large Dynamical Systems
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Zmejev D.N., Levchenko N.N., Okunev A.S., Klimov A.V.
The architecture of scheduler of mapping processor of PDCS "Buran"
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Prokopenko N.N., Butyrlagin N.V., Pakhomov I.V.
The main parameters and equations of basic configurations multidifferential operational amplifiers with high impedance node
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Pugachev A.A., Ivanova G.A.
The method for photosensitive matrix VLSI modulation transfer function simulation
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Gourary M.M., Rusakov S.G., Ulyanov S.L.
The method of harmonic balance for electrothermal analysis of periodic steady states of IC
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Ryzhova D.I., Gavrilov S.V.
The method of peak current estimation at logic level taking into account simultaneous switching of inputs
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Volobuev P.S., Gavrilov S.V., Ryzhova D.I.
The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control
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Stempkovsky A.L., Amerbaev V.M.
The principle of factorization in a problem of design of RBS-based processors
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Chaplygin Yu.A., Adamov Yu.F., Timoshenkov V.P.
Using of VBIC model for SiGe integrated circuit application
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| 2016 | |
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Shlepnev A.A.
Adoption of Genetic Algorithms for running in elastic compute environment concerning CAD applications
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Klimov A.V., Okunev A.S.
A graphical dataflow meta-language for asynchronous distributed programming
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Zelenko G.V., Ivannikov A.D., Roschin A.V., Stempkovsky A.L.
Algebraic Decomposition Models for Digital System Design Debugging by Simulation
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Matyushkin I.V.
Algorithms of the parallel computations in the formalization of cellular automata: the sorting of strings and the multiplication of numbers by Atrubin’s method
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Calem M.M., Nematov M.G., Uddin A., Panina L.V., Morchenko A.T., Skidanov V.A.
Amorphous glass-coated microwires for applications as embedded stress sensors in functional materials
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Matyushkin I.V., Zapletina M.A.
Cellular automata methods of the numerical solution of mathematical physics equations for the hexagonal grid
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Telpukhov D.V., Solovyev R.A., Balaka E.S., Rukhlov V.S., Mikhmel A.S.
Design features of the multipliers on the module using advanced CAD
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Zmejev D.N.
Design tools of high-performance dataflow computing systems
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Djigan V.I.
Fast Affine Projection Algorithm: Full Version
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Ostrovskaya N.V., Skidanov V.A., Iusipova Iu.A.
Features of magnetization reversal in a MRAM cell — I. In-plane anisotropy
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Ostrovskaya N.V., Skidanov V.A., Skvortsov M.S.
Features of magnetization reversal in a MRAM cell — II. Perpendicular anisotropy
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Lyalinsky A.A.
Generation of large sets of logical functions for digital integrated circuits CAD systems
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Garbulina T.V., Lyalinskaya O.V., Khvatov V.M.
Improving the efficiency of the design integrated circuits on FPGA with limited resources to trace
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Prokopenko N.N., Chernov N.I., Yugai V.Ya., Butyrlagin N.V.
Linear Synthesis of k-valued Digital Structures: Principle of Generalization
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Rakitin V.V., Rusakov S.G.
Memristor oscillator Schmitt trigger with multiple steady states of dynamic equilibrium
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Sapogin V.G., Prokopenko N.N., Ivanov Y.I., Bugakova A.V.
Nano-dimensional effect at planar inductance with “conducting film inside current ring”-technology
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Gavrilov S.V., Zhukova T.D., Ryzhova D.I.
Optimization methods of coding circuits based on the binary decision diagrams for synthesis of fault-tolerant micro- and nanoelectronic circuits
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Gourary M.M., Zharov M.M., Rusakov S.G., Ulyanov S.L., Lyalinsky A.A.
Parameter optimization subsystem of CMOS operational amplifiers
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Stempkovsky A.L., Telpukhov D.V., Solovyev R.A., Telpukhova N.V.
Probabilistic methods for reliability evaluation of combinational circuits
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Gourary M.M., Zharov M.M., Ulyanov S.L., Khodosh L.S.
Rational Transfer Functions Approximation on the Base of Integral Accuracy Criterion
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Gourary M.M., Zharov M.M., Ionov L.P., Mukhin I.I., Rusakov S.G., Ulyanov S.L.
Simulation of PLL Perturbation Based on Blocks Transfer Functions
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Dvornikov O.V., Prokopenko N.N., Bugakova A.V., Ignashin A.A.
The Instrumentation and Differential Difference Amplifiers of Sensor Systems Based on the New Microcircuit of the Structured Array MH2XA010
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Gurov S.I., Ryzhova D.I.
The algorithm for synthesis of digital ICs based on the Gilbert decomposition
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Klimov A.V., Levchenko N.N., Okunev A.S., Stempkovsky A.L.
The application and implementation issues of dataflow computing system
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Adamov Yu.F., Balaka E.S., Rukhlov V.S.
The circuitry of electronic devices that operate in conditions of electromagnetic noise
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Zmejev D.N., Klimov A.V., Levchenko N.N.
The means for computation distribution in the PDCS "Buran" and the implementation variants of a block of hash-functions
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Kononov A., Pugachev A.A.
The method for CMOS APS light-voltage characteristics technological-device modeling
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Zheleznikov D.A., Lyalinsky A.A.
The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism
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Gavrilov S.V., Zhukova T.D., Ryzhova D.I.
The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistor’s gate
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Zmejev D.N., Kuzmin E.N., Levchenko N.N., Okunev A.S.
Trends in development of content addressable memory architectures and its application in the parallel dataflow computing system
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| 2018 | |
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Levchenko N.N., Okunev A.S., Stempkovsky A.L.
Advantages of Dataflow Computing Model
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Ryzhova D.I., Vasilyev N.O., Zhukova T.D.
Algorithm of Inter-gate Resynthesis at the Transistor Level for Computer-aided Design of Microelectronic Circuits
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Andreev A.E., Rusakov A.S., Yahontov A.
Analytical Timing Driven Global Placement of Structured ASIC
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| | |
Klimov A.V., Levchenko N.N.
Branches in the Dataflow Metalanguage UPL (METAL) and Methods of their Implementation in the PDCS “Buran”
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| | |
Matyushkin I.V., Zapletina M.A.
Cellular Automata Computational Parallelism of Elementary Matrix Operations
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Lyalinsky A.A.
Characterization of Analog Circuits Based on Cloud Computing
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Telpukhov D.V., Zhukova T.D., Demeneva A.I., Gurov S.I.
Circuit of the Functional Control for Combinational Circuits Based on R-code
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Dvornikov O.V., Tchekhovski V.A., Diatlov V.L., Prokopenko N.N., Budyakov P.S.
Design of Voltage Comparators Based on the Elements of the Radiation-Hardened Low-Temperature BiJFET Array Chip MH2XA030
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Zmejev D.N., Okunev A.S.
Development and Investigation of Algorithm of Sparse Matrices Multiplication Task for the Parallel Dataflow Computing System "Buran"
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Tiunov I.V., Lipatov I.A., Zheleznikov D.A.
Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs
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Telpukhov D.V.
Development of Methods for Genetic Synthesis of Fault-Tolerant Logic circuits
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Nadolenko V.V., Telpukhov D.V., Bitkov U.
Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits
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Ostrovskaya N.V., Skidanov V.A., Iusipova Iu.A.
Dynamics of Magnetization in the Free Layer of a Spin Valve Under the Influence of Magnetic Field, Perpendicular and Parallel to the Layer Plane
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Khvatov V.M., Garbulina T.V., Lyalinskaya O.V.
Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs
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Denisenko D.Yu., Prokopenko N.N.
Low-Sensitivity Active RC-filter of the Second Order with an Extended Frequency Range
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Zmejev D.N., Klimov A.V., Levchenko N.N., Okunev A.S.
Methods for Computation Planning in the Parallel Dataflow Computing System "Buran"
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Pugachev A.A., Ivanova G.A.
Modulation Transfer Function Model for Photosensitive VLSI Under One Single Impact Particle Event
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Lyalinsky A.A.
Optimization Procedures in the Analog Circuit CAD System
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Gavrilov S.V., Zheleznikov D.A., Chochaev R., Khvatov V.M.
Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip
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Ivannikov A.D.
Research and Development of Digital System Block Models Based on Their Description as a Stationary Dynamical System Family
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Gourary M.M., Zharov M.M., Rassadin A.E., Rusakov S.G., Ulyanov S.L.
Simulation of Circuits with Ferroelectric Capacitances
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Ostrovskaya N.V., Skvortsov M.S., Skidanov V.A., Iusipova Iu.A.
Simulation of Magnetization Dynamics in Three-layered Ferromagnetic Structures with Pinned Boundaries
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Gourary M.M., Zharov M.M., Rusakov S.G., Ulyanov S.L.
The Application of Single-step High Order Integration Methods for Periodic Steady-state Analysis of Integrated Circuits
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Gourary M.M., Zharov M.M., Ionov L.P., Mukhin I.I., Ten I.M., Ulyanov S.L.
The Characterization Flow and Simulation Method of Frequency Synthesizer
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Butyrlagin N.V., Chernov N.I., Prokopenko N.N., Yugai V.Ya.
The Design of Current Memory Elements Based on the Mathematical Tool of Linear Algebra
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Zheleznikov D.A., Zapletina M.A., Khvatov V.M.
The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs
|
| | |
Rakitin V.V.
The Symmetrized Memristor Relaxation Oscillator
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Solovyev R.A., Kustov A.G., Rukhlov V.S.
The Technique for Implementing a Neural Network for Recognizing Handwritten Digits in FPGAs Based on Fixed Point Calculations
|
| | |
Djigan V.I.
Two-dimensional Adaptive Antenna Arrays in Complex-valued and Real-valued Arithmetic
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| 2020 | |
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Ivannikov A.D., Stempkovsky A.L.
Analysis of Iterative Methods for Solving Logical Equation Systems and their Use in Digital System Simulation
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Zhukov D.V., Zheleznikov D.A., Zapletina M.A.
Application of SAT Approach to Switch Blocks Routing for Reconfigurable System-on-a-chip
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| | |
Pilipenko A.M., Prokopenko N.N., Budyakov P.S.
Application of the template model for approximation of differential characteristics of complementary JFETs
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Ilin S.A., Korshunov A.V., Garbulina T.V.
Benchmarking Energy Efficiency of Libraries on FinFET 7nm
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| | |
Kurganov V.V., Djigan V.I.
Calibration of Antenna Arrays with Small Number of Antennas: Problems and Solutions
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Rakitin V.V.
Chaotic memristor oscillator with switching capacitor amplifier
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| | |
Lyalinsky A.A.
Characterization of FPGA-based Digital Libraries
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Mikhmel A.S., Mkrtchan I.A., Telpukhov D.V.
Development of Special Logic Element Models for Timing Analysis of Reconfigurable System-on-a-Chip
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| | |
Zhukova T.D.
Development of a computer-aided design system based on redundant coding methods
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| | |
Djigan V.I.
Direct Learning Digital Predistorters for Power Amplifiers
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Bobkov S.G.
Directions and methods for improving the performance of microprocessors
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| | |
Iusipova Iu.A.
Energy efficiency and performance of spin-valve structures in MRAM and HMDD
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| | |
Gourary M.M., Rusakov S.G.
Features of the application of envelope methods for the analysis of autonomous oscillators
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| | |
Ostrovskaya N.V., Skidanov V.A.
Field-like torque-component influence on the magnetization dynamics in the three-layered nanostructure
|
| | |
Djigan V.I.
Fractionally Spaced Feed-Backward Equalizers, based on Fast RLS Adaptive Filtering Algorithms
|
| | |
Iusipova Iu.A.
Frequency and amplitude characteristics of STNO based on a spin valve with planar and perpendicular layer anisotropy
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Ivannikov A.D.
Function test set formation for design correctness checking
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Rukhlov V.S., Solovyev R.A., Kustov A.G.
Hardware and software solutions to increase the reliability of combinational logic in the FPGA basis without taking into account interconnections and the I/O blocks
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| | |
Zmejev D.N., Levchenko N.N., Okunev A.S., Stempkovsky A.L.
Impact of features of the computing model and architecture on the reliability of the parallel dataflow computing system
|
| | |
Vasilyev N.O., Tiunov I.V., Ryzhova D.I.
Logic Resynthesis Method in the FPGA Design Flow
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| | |
Zmejev D.N., Levchenko N.N., Okunev A.S.
Methods and approaches to improving the reliability of the parallel dataflow computing system
|
| | |
Gourary M.M., Rusakov S.G.
Parametrized Kuramoto Model for Coupled Oscillators with Fractional Frequencies Ratios
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| | |
Drozdov D.G., Prokopenko N.N., Savchenko Ye.M., Dukanov P.A., Grushin A.I.
Research of high-voltage complementary junction field-effect transistors over a range of temperature using methods of TCAD process/device modeling
|
| | |
Tiunov I.V.
Resynthesis methods for FPGAs based on cells with separated outputs and built-in feedback
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| | |
Gavrilov S.V., Khvatov V.M., Zheleznikov D.A., Garbulina T.V.
Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip
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| | |
Dvornikov O.V., Tchekhovski V.A., Prokopenko N.N., Galkin Ya.D., Kunts A.V.
Taking into Account the Simultaneous Effect of Low Temperatures and Penetrating Radiation on the Characteristics of the Bipolar and JFETs in the Circuit Simulation
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| | |
Zapletina M.A., Zheleznikov D.A., Gavrilov S.V.
The Hierarchical Approach to Island Style Reconfigurable System-on-a-chip Routing
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| | |
Gourary M.M., Zharov M.M., Rusakov S.G., Ulyanov S.L.
The adaptive algorithm for the analysis of oscillatory circuits
|
| | |
Frolova P.I., Chochaev R., Ivanova G.A., Gavrilov S.V.
Timing-driven placement algorithm based on delay matrix model for reconfigurable system-on-chip
|
| | |
Klimov A.V.
Tools for verification of computation distribution in the Parallel Dataflow Computing System (PDCS) “Buran”
|
| | |
Lyalinsky A.A.
Web-based Characterization of Digital Libraries
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| 2021 | |
| | |
Djigan V.I., Kurganov V.V.
Accuracy of Phase-Less Algorithms of Antenna Array Calibration
|
| | |
Dvornikov O.V., Tchekhovski V.A., Prokopenko N.N., Galkin Ya.D., Kunts A.V., Chumakov V.E.
Analog integrated circuits design for extreme environmental conditions on the base of master slice array MH2XA031
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| | |
Telpukhov D.V., Zhukova T.D., Kretinina P.D.
Analytical Method for Choosing the Most Efficient Algorithm for Fault-Tolerant Combinational Circuits Synthesis
|
| | |
Stempkovsky A.L., Bobkov S.G., Zmejev D.N., Levchenko N.N., Klimov A.V.
Automated Optimal Configuration Determination of the Parallel Dataflow Computing System for Solving a Specific Problem
|
| | |
Klimov A.V.
Automatic Differentiation in a Dataflow Language on the Example of a Deep Learning Problem
|
| | |
Rubis P.D., Matyushkin I.V.
Cellular-automaton algorithm of matrices permutation with an oscillatory scheme of element shift
|
| | |
Gourary M.M.
Compact model generation for distributed parameter systems
|
| | |
Frolova P.I., Chochaev R.
Development and Comparative Analysis of Initial Placement Methods for FPGA
|
| | |
Ivannikov A.D., Stempkovsky A.L.
Digital Block Mathematical Model for the Joint Hardware and Software/firmware Simulation System
|
| | |
Kuzminova T.D., Khvatov V.M., Zheleznikov D.A.
Formation of the reduced logical elements library for FPGA
|
| | |
Dvornikov O.V., Pavluchik A.A., Prokopenko N.N., Tchekhovski V.A., Kunts A.V., Chumakov V.E.
GaAs analog master slice
|
| | |
Ostrovskaya N.V., Skidanov V.A., Iusipova Iu.A.
Mathematical Model of the SOT-MRAM Cell based on the Spin Hall Effect
|
| | |
Zapletina M.A.
Methods for speeding up the modified Pathfinder routing algorithm for island-style FPGA
|
| | |
Gourary M.M., Rusakov S.G., Ulyanov S.L.
Numerical Technique of Noise Analysis based on Two-Level Mixed Frequency–Time-models for Circuit Simulators
|
| | |
Ilin S.A., Zapletina M.A., Lastochkin O.V.
Optimization of Standard Cells Power Consumption: Logical Effort Based Algorithm
|
| | |
Ivannikov A.D.
Organization of Debugging Process for Digital Microelectronic System Designs
|
| | |
Telpukhov D.V., Nadolenko V.V.
Reliability-Driven Logic Synthesis Using Arbitrary Standard Cell Library
|
| | |
Ivannikov A.D.
Structure Formalization of Management Information System Software
|
| | |
Gourary M.M., Rusakov S.G., Ulyanov S.L.
The Development of Multi-terminal Element Model with Arbitrary Number of Terminals for Circuit Simulator
|
| | |
Rusakov S.G., Ulyanov S.L.
The Steady-State Analysis of Integrated Circuits Using Homotopy Methods
|
| 2022 | |
| | |
Djigan V.I.
Adaptive Equalization of Frequency Response of Acoustic Wave Propagation Channels in Closed Rooms
|
| | |
Rakitin V.V., Rusakov S.G., Ulyanov S.L.
Analysis of Coupled Memristor based Oscillators using Circuit Simulators
|
| | |
Frolova P.I., Khvatov V.M., Chochaev R.
Comparative Analysis of Clustering and Placement Methods for Reconfigurable System-on-Chips
|
| | |
Stempkovsky A.L., Telpukhov D.V., Zhukova T.D.
Development of Concurrent Error Detection Circuit Based on Automated Generation of Error-Correcting Code
|
| | |
Goglev G.I., Tiunov I.V.
Development of a Digital Integrated Circuits Visualization Algorithms at the Gate Level
|
| | |
Lebedev O.B., Lebedev B.K., Schelokov A.N.
Distribution of connections by layers in multi-layer global routing
|
| | |
Samoilov L.K., Prokopenko N.N., Denisenko D.Yu.
Dynamic Errors of Band-pass Bessel Filters Switched on at the ADC Input
|
| | |
Prokopenko N.N., Dvornikov O.V., Chumakov V.E., Kleimenkin D.V.
Gallium arsenide operational amplifiers with transconductance multipliers of input differential stages
|
| | |
Lyalinsky A.A.
Generation of Logical Function Libraries
|
| | |
Kustov A.G., Solovyev R.A., Stempkovsky A.L., Telpukhov D.V.
Hardware Implementation of a Neural Network for Object Detection in FPGA
|
| | |
Zhigulin A.S., Solovyev R.A.
Hardware Implementation of an Accelerated Approximated Matrix Multiplier Based on MADDNESS Algorithm
|
| | |
Levchenko N.N., Zmejev D.N.
Implementation of Majority Function Based on Matching Processor in the Parallel Dataflow Computing System "Buran"
|
| | |
Stempkovsky A.L., Telpukhov D.V., Mkrtchan I.A., Solovyev R.A.
Implementation of an RNS Reverse Converter for General Moduli Sets Based on LUTs with Reference Points
|
| | |
Iusipova Iu.A., Ostrovskaya N.V., Skidanov V.A.
Mathematical model of a cylindrical SOT-MRAM cell
|
| | |
Rusakov S.G., Gourary M.M.
Method of Merging Models to Analyze the Synchronization Modes of Coupled Oscillators
|
| | |
Lyalinsky A.A.
Methodology for the Effective Construction of Large Tables
|
| | |
Ivannikov A.D.
On mathematical models of digital microelectronic systems and verification of the sequence of functions performed at the design stage
|
| | |
Levchenko N.N., Zmejev D.N.
Research of Various Options for Implementing Program Construction «Loop» in Dataflow Computing Model
|
| | |
Nadolenko V.V.
Three level logic minimization using graphics processing units
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