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The block of self-testing of internal memory
Authors
	Bobkov S.G.
	Evlampiev B.E.
	Sidorov A.Yu.
Date of publication
	2005
Abstract
	Paper is devoted to a problem of testing of blocks of the memory which are a part of microcircuits of limiting speed. Such blocks of memory can have different quantity of ports of writing and ports of reading, and also different word length of ports. Therefore for testing such blocks it is impossible to use commercially accessible CAD. For the solution this problem the architecture of the block of self-testing is proposed, the parametrical model in language of the description of equipment Verilog HDL is developed and debugged, the software for carrying out of testing with use of JTAG-protocol is developed and debugged. The offered architecture of the block of self-testing is used for testing arrays of memory of the microprocessor.
Keywords
	self-testing of internal memory
Library reference
	Bobkov S.G., Evlampiev B.E., Sidorov A.Yu. The block of self-testing of internal memory // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 222-228.
URL of paper
	http://www.mes-conference.ru/data/year2005/33.pdf