| CMOS circuit interval static timing analysis accounting for logic correlations |
|
|
| Authors |
| | Gavrilov S.V. |
| | Gudkova O.N. |
| | Severtsev V.N. |
| Date of publication |
| | 2012 |
|
| Abstract |
| | The 45-32nm process level VLSI design requires fundamental modifications both for design methodology and CAD tools. This paper is dedicated to the development of the new IP-block performance analysis account for logic correlation in interval simulation. The choice of the interval approach is conditioned by the considerable parameter variation weight increasing for nanometer element performance evaluation. |
| Keywords |
| | Intellective property IP-block, logic-timing analysis, SP-DAG, static timing analysis. |
| Library reference |
| | Gavrilov S.V., Gudkova O.N., Severtsev V.N. CMOS circuit interval static timing analysis accounting for logic correlations // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 113-118. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2012/pdf/D15.pdf |
