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Improving the efficiency of the design integrated circuits on FPGA with limited resources to trace
Authors
	Garbulina T.V.
	Lyalinskaya O.V.
	Khvatov V.M.
Date of publication
	2016
Abstract
	At the present time domestic developments are coming to replace foreign field programmable gate arrays (FPGAs). Existing computer-aided design (CAD) support the development of specific FPGA manufacturers (Xilinx, Altera, Actel) and do not provide the opportunity to design FPGA with new architecture. The purpose of this work is the development of the design flow, applicable to any FPGA architecture, and improving the efficiency of the design of integrated circuits on domestic FPGA using specially developed linguistic means on the basis of language TCL. During the study developed and implemented software tools for the optimal placement of device components and trace their interconnections with a modified algorithm PathFinder. Simulation results show the effectiveness of the developed algorithms.
Keywords
	CAD, TCL, routing, placement, PathFinder.
Library reference
	Garbulina T.V., Lyalinskaya O.V., Khvatov V.M. Improving the efficiency of the design integrated circuits on FPGA with limited resources to trace // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 165-171.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D126.pdf