Design features of the multipliers on the module using advanced CAD

Telpukhov, D.V.; Solovyev, R.A.; Balaka, E.S.; Rukhlov, V.S.; Mikhmel, A.S.

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Design features of the multipliers on the module using advanced CAD

Authors

Date of publication

2016

Abstract

This work is devoted to the analysis of different approaches to modular multiplier design using modern CAD systems. Internal CAD libraries contain optimized architectural solutions for functional blocks, which can be selected depending on the device input constraints. As there are no such decisions for modular devices in the libraries, we have to estimate which of the many developed functional block implementations are the most effective.
In this paper methods of implementing modulo multipliers are investigated and their performance characteristics and hardware costs are studied. In course of work, six most popular architectures of modulo multipliers have been analyzed. To evaluate their effectiveness for two technological bases (CAD Quartus II FPGA Altera and Synopsys Design Compiler for ASIC), two-input multipliers were synthesized for a wide range of basic modules.
Based on these experiments, we can highlight look-up table multiplier implementation as the most area-consuming. Moreover, if for VLSI circuits the use of this method is justified by their excellent performance, for FPGA circuits this method is not justified either with regard to delay, or, even more so, with regard to area. It should also be noted that for FPGA circuit the number of logic gates we can use is a serious limitation. Generally, the results show similar trends for both VLSI and FPGA, which confirms the versatility of the presented methods. Experiments have shown that normally the best method to build modulo multipliers for VLSI is the index method, and for FPGA - difference of squares method

Keywords

Residue Number System, RNS-based multiplier, FPGA, VLSI.

Library reference

Telpukhov D.V., Solovyev R.A., Balaka E.S., Rukhlov V.S., Mikhmel A.S. Design features of the multipliers on the module using advanced CAD // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 249-254.

URL of paper

http://www.mes-conference.ru/data/year2016/pdf/D040.pdf