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Optimization of Standard Cells Power Consumption: Logical Effort Based Algorithm  

Authors
 Ilin S.A.
 Zapletina M.A.
 Lastochkin O.V.
Date of publication
 2021
DOI
 10.31114/2078-7707-2021-3-34-38

Abstract
 Latency and power consumption are the key controlled characteristics in a digital design flow for standard cells. The paper proposes a method that uses the Power-Delay Product (PDP) as an objective function. A mathematical model is built to minimize PDP by scaling the gates sizes. The results are obtained for the CMOS 28 nm technology on the example of a net of three and five inverters, a combinational circuit and a one-bit adder circuit. Both parts of the objective function were presented in terms of the Logical Effort methodology. The search for the minimum of the objective function was performed. The proposed solution is based on the assumption that the correction value is identical for all circuit gates. The proposed method is used to simplify solving the optimization equation and to give an acceptable result in comparison with traditional scaling methods with a focus on the performance. The main aim of the work is to show that redefining the electrical load of the gates makes possible to reduce the power consumption with an increase in the delay. An achieved decrease in power was 28% and 30%, PDP decrease was 24% and 18% for 3 and 5 gates length circuits with an increase in delay of 6.7% and 17%, respectively. For a single-bit adder circuit, the proposed model demonstrated a 33% reduction in power and 15% in PDP with a 9% increase in average latency.
Keywords
 Power Delay Product, Logical Effort, Standard Cell Library, Optimization.
Library reference
 Ilin S.A., Zapletina M.A., Lastochkin O.V. Optimization of Standard Cells Power Consumption: Logical Effort Based Algorithm // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 3. P. 34-38. doi:10.31114/2078-7707-2021-3-34-38
URL of paper
 http://www.mes-conference.ru/data/year2021/pdf/D029.pdf

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