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Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs
Authors
	Tiunov I.V.
	Lipatov I.A.
	Zheleznikov D.A.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-1-69-74
Abstract
	With increasing complexity of the circuits designed for FPGAs, the occupied area also grows. This leads to difficulties in the stages of placement and tracing due to the limited traceability of the FPGA resources. Thus, there is a growing need to apply logical resynthesis and optimization algorithms, which should lead to a reduction in occupied area. In our previous work [1] we described an architecture-oriented algorithm for optimizing circuits, which resulted in the combination of logic elements of the circuit with triggers on the example of FPGAs of the family 5510XC. Then the simplest variant was considered, when one trigger is connected to one logic element only by the data input. In this paper, we describe optimization methods for cases where several elements, both logic and triggers, are connected to the output of a single logical element. The method was tested on a set of test digital circuits, and the results are arranged in a comparative table. In the introduction, we recall the results of our past work and point out the limitations of the previous optimization method. The second chapter describes an ideal FPGA cell, for which the transformations described in the article are possible. The real cells of FPGAs differ from the ones presented, but they have a part of its capabilities. For each trigger input, there is a multiplexer in the cell that allows to connect the LUT output to one of the corresponding trigger inputs. This opens the door to further optimizations. In addition, the cell must have two outputs: the output of the trigger and the output directly from the LUT. In the third chapter, we talk about improving the optimization method from our past work. The essence of the improvement is that, taking into account the peculiarities of an ideal cell, the combination of LUT and the trigger can be performed not only on the data input, but also on the control inputs: clock, reset and set. The fourth chapter describes one more optimization method proposed by us, when several elements are connected to the load, among which there are one or several triggers. LUT in this case is combined with one or several (with creating copies of LUT) triggers. The remaining elements are connected as a load to the combined element to the output of the LUT. The fifth chapter presents the results of the work of resynthesis algorithms for both the ideal FPGA cell and the real FPGA with which our institute operates. In conclusion, the results of the work are obsolete.
Keywords
	technology mapping, logical resynthesis, design flow, digital circuit, CAD, FPGA.
Library reference
	Tiunov I.V., Lipatov I.A., Zheleznikov D.A. Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 69-74. doi:10.31114/2078-7707-2018-1-69-74
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D106.pdf