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The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs  

Authors
 Zheleznikov D.A.
 Zapletina M.A.
 Khvatov V.M.
Date of publication
 2018
DOI
 10.31114/2078-7707-2018-1-188-192

Abstract
 In this work we proposed and investigated a several ways to implement the rip-up and reroute technique for the automatic interconnect routing. Interconnect routing step is a very important part of the circuit design flow in the basis of reconfigurable system-on-a-chip (RSoC) «Almaz-14». This RSoC is a domestic development of JSC Molecular Electronics Research Institute and Mikron PJSC, based on the classical hierarchical field programmable gate array (FPGA). In addition to FPGA, this RSoC includes different types of macro blocks, such as phase-locked loop (PLL) blocks, multipliers, and blocks of external configurational memory. The algorithm for circuit interconnect routing is based on the algorithm A*. This is the modification of a classical algorithm of searching shortest path on graph (Dijkstra’s algorithm). In the context of this algorithm, the rip-up and reroute technique is a combinatorial task of sorting and ordering nets array by changing routing priority to find the optimal configuration. Here an attempt has been made to determine the limits of applicability and to estimate the overall efficiency of some simple tricks for rip-up and reroute technique. Some advantages, limitations, problems and features of each of them are reviewed and discussed.
Keywords
 interconnect routing, computer-aided design, Field-Programmable Gate Array (FPGA).
Library reference
 Zheleznikov D.A., Zapletina M.A., Khvatov V.M. The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 188-192. doi:10.31114/2078-7707-2018-1-188-192
URL of paper
 http://www.mes-conference.ru/data/year2018/pdf/D069.pdf

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