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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 to 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 year

All topics ADC design problems Cellular automata Design of System-on-chip (SoC) and IP-blocks Design of VLSI elements Design of VLSI signal processors Design of analog and mixed functional blocks of VLSI Design of digital functional blocks of VLSI Design of fault-tolerance systems Design of micro-electromechanical systems Design of nanoelectronic devices Design of nanoelectronic devices based on Josephson junctions Design of photodetecting VLSI Design of radiation-resistant VLSI Design of technological processes Designing components for aerospace and navigation technology Genetic algorithms in VLSI CAD Methods and algorithms for automated layout design Methods for high-level simulation Methods of device technology simulation of VLSI Methods of digital information processing and digital filters Methods of electro-thermal simulation Methods of logic synthesis and functional logic simulation ... Methods of simulation of VLSI electrical characteristics Models of devices for circuit simulation Neural networks Problems of development of sensory microcircuitry Simulation of data transfer channels Study of the magnetic properties of materials Unconventional computing systems Web-based VLSI CAD design of memory cells

Selection on topic: Design of digital functional blocks of VLSI

Selected papers: from 2005 to 2024 year

In selection - 154 papers

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C

D

E

F

H

I

L

M

N

O

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W

6

A
	A 4-channel Multi-standard Adaptive Serial Transceiver for the Range 1.25-10.3Gb/s in CMOS 65nm A 65-nm Implementation of Tandem-Style Fractional-N Synthesizer for video controller A Fast Method of Generating Pseudo-Random Vectors of High Dimension for testing Systems-on-Chip A High Speed Level Shifter for High Voltage Supply Range with High Reliability A Library of Self-Timed Elements or ASIC-Technology ASMD-FSMD Technique for Digital Device Design Accurate High-speed Frequency Meter for Doppler Initial Velocity Measurement Adaptation of performance tests for the 64-bit universal superscalar microprocessor Adaptation process of System-on-a-Chip RTL-description for distributed emulation system Alarm controllers MS-0226 and ÌÑ-0226G on the basis of platform "MULTICORE" Algorithmic Design of Digital Operational Units with Low Power Consumption Algorithms for Functional Correction of Boolean Circuits A method for reducing timing delay temperature dependence of digital integrated circuits A methodology for testing the microprocessor core of a system on chip with a x86-compatible microprocessor Analysis of circuit solutions for integrated microwave digital step attenuators manufactured by various technological processes Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI An integrated LDO regulator for self-powered systems Architecture and structural-topological features of bit-stream devices Architecture of the unified computing block for contactless photon system of measurement of parameters of a rail track Architecture validation tests for RTL-model of 64-bit superscalar microprocessor Arithmetical algorithms of the coding system of 1 from 4 with an active zero and estimation of the parameters of high-speed performance and occupied area of the unit of summation Automated Optimal Configuration Determination of the Parallel Dataflow Computing System for Solving a Specific Problem
B
	Block FIR filter implementation with a data-flow recurrent signal processor Built-in self-repair for SRAM with redundant elements
C
	“Cycle-To-Cycle” methodology for timing analysis of high speed synchronous interfaces CAVLC encoder IP-core for H.264/AVC Circuit Design of Synchronizing Devices Within High-speed Data Services Circuit of the Functional Control for Combinational Circuits Based on R-code Clock Tree Synthesis Optimization Common approaches to the FPU verification Communication fabric IP-core for a system-on-chip Complex arithmetic coprocessor
D
	DC-DC Converter Conducted Emission Level Estimation at Design Stage Debugging of the block of transformation of addresses of the microprocessor Delay-Insensitive Floating Point Multiply-Add-Subtract Unit Design a functional model of FPGA whith single-driver technology in Xilinx ISE system Design and investigation of the Hall element on 180 nm technology Designing a Configurable 32-Bit RISC-V Microprocessor Designing on FPGA and SoC high-performance binary comparators of a big dimensionality Design of All-digital Phase-locked Loop Design of Power Efficient 14-port Register File and Translation Lookaside Buffer in 28-nm Process Design of Self-Timed Circuits: a Functional Approach Design of digital CMOS circuits for extreme temperatures Design of the error-correcting code blocks using the two-phase CMOS logic elements Design of the hybrid CAM register Design principles for fault-tolerant random access memory for space applications Development and approbation of the method of microcircuits interchangeability efficiency evaluation in radar equipment based on critical circuit and parametric characteristics set Development of FPGA Project for Microprocessor Prototype Module Development of a Digital Integrated Circuits Visualization Algorithms at the Gate Level Development of integral digital filters for sigma-delta converters using MATLAB Digital Block Mathematical Model for the Joint Hardware and Software/firmware Simulation System Digital Signal Processor With Non-Conventional Recurrent Data-Flow Architecture Dynamic modification of embedded devices internal firmware for solve reverse engineering problems
E
	Electrostatic Discharge Exposure on the Transistor in Consideration of Seat Capacitance Error control coding for submicron dynamic RAM Evaluation of the use of systolic arrays in the implementation of matrix multiplication algorithms on FPGAs Exact Synthesis of Low Precision Multipliers for Intel FPGAs Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array
F
	FPGA prototyping for functional verification of multi-core processors Fast Multipliers for Hardware Implementation of Artificial Neural Networks Fast and Efficient Approach and Its implementation Study for the Design of Wave Components Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC Floating point and complex arithmetic coprocessors and their verification Functional Test for Graphics Controller Functional verification of microprocessors using machine-learning methods
H
	Hardening Self-Timed Circuit Indication against Soft Errors Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words Hardware Implementation of an Accelerated Approximated Matrix Multiplier Based on MADDNESS Algorithm High-speed content addressable memory block design
I
	Implementation of a Control Device for a Railway Switch Electric Drive on FPGA Implementation of the combustion problem main functions based on specialized vector coprocessor FMA operations Improving the Analysis of the Propagation of Impulse Signals in Structures of N Cascades of Coupled Lines Improving the Efficiency of Automated Monolithic Integrated Circuits Visual Inspection Algorithm Increasing the Speed of a Multi-bit Binary Multiplier Inexact operation prediction scheme realized in multiply-add fused module Instruction scheduling for vector processors with variable vector length Investigation of CMOS Multiplexor SEL Sensitivity at Low Temperature Investigation of High-Precision Laser Instrument for Fabrication of Integrated Circuits and Monitoring of Seismic and Gravitational Processes Investigation of the Characteristics of the Components of Synchronization Devices for High-speed Data Transmission Systems
L
	Leakage Power IC Optimization without RTL Changing Library composition optimization for self-timed circuit synthesis
M
	Method and means of built-in self-testing of memory chip Method for Organizing the Moore Automaton with the Increased Resistance to Soft Failures Methodology for creating design-for-test for CMOS VLSI Methodology for the Effective Construction of Large Tables Methodology of calculating dependent timing constraints for libraries of standard digital cells Methodology of the optimization and efficiency evaluation for the Secondary Cache Methods for Fast Implementation of Loading in Computing Systems Methods of increase of productivity of the superscalar RISC-processor Microcontroller 1830ÂÅ32Ó – 8-bit MSC-51 architecture in radhard style Microstrip directional coupler directivity improvement Modification of the High Bandwidth Solid State Drive Controller within the multi-stage architecture Motion Estimation IP-core Implementation for H.264 Full HD Video Codec Multi-pipelined architecture of high-performance crypto-blocks for using in “Systems on a Chip”
N
	NAND Flash memory controller IP-core
O
	On mathematical models of digital microelectronic systems and verification of the sequence of functions performed at the design stage On the formal specification of digital systems Optical Receiver Architecture for Microprocessor Systems Optimization of Standard Cells Power Consumption: Logical Effort Based Algorithm Optimization of structure of controllers of serial buses. The solution of problems of lack of pins of a integrated circuit and loading of the processor at data transmission Optimizing the prefetch mechanism in the secondary cache memory Organization of Debugging Process for Digital Microelectronic System Designs
P
	Parameterizable matrix multiplier of fixed-point binary numbers in direct and complementary code Pipeline Depth Influence on DSP Performance Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode Planar printed antenna array for Doppler speed and drift angle meter Problems of creation of computers of series "Baguet" for problems with increased requirements to reliability of long-term functioning Processing speed increase and hardware cost reduction in Hsiao decoders
R
	Random Test Generator for Multicore Microprocessor Cache Coherence Verification (Ristretto) Rank codec IP-core Readout circuit from the nonvolatile memory Register Duplication for Scan Compression Designs Register file base elements and design flow development for SOI 0.25-micron technology Remote Stand for Synchronous Operation with FPGA-based Equipment Research of hardware implementation efficiency of discovering data dependences in coprocessor's pipeline of KOMDIV128-RIO processor Resonant energy efficiency driver Resource-aware Patch Generation of Boolean Circuits Resynthesis methods for FPGAs based on cells with separated outputs and built-in feedback Route of effective IC development
S
	SATOK - System for Self-Timed Integrated Circuits Testing SRAM memory controller to maximize switch performance Schematic-topological design of VLSI cells Search for a rational structure of a test generator for subsystems of built-in self-testing of digital circuits Self-Timed Computing Device for High-Reliable Applications Self-Timed Floating Point Multiply-Add Unit Self-Timed Multiplier Performance Improvement Technique Self-timed D-trigger with «Load/Latch» Set of integrated circuits designed to control power transistor switches Single Precision Reciprocal and Inverse Square Root Functions Modules Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects Standalone verification of microprocessors using reference models with various levels of abstraction Synthesis external interrupt controller with dynamically change the priority Synthesis of multiprocessor computing structures based on models of models System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture
T
	TCAD Study of Responsivity of n-channel MOS Dosimeter Fabricated in CMOS Processes Technometric Identification of Integrated Circuits for Controlling Life Cycle and Counterfeit Detection Testing the Performance of the Embedded Gigabit Ethernet Controller’s FPGA Prototype when working with TCP The Concurrent Error-Detection Circuit Typical Structure Based on Boolean Correction and Calculations Control by Two Diagnostic Parameters in the Experiment The Electromagnetic Interferences From Display Device on Capacitive Touch Panel The Functional Method of the Analysis of Speed-Independent Circuits of Any Size The block of self-testing of internal memory The implementation of channels of DDR4 RAM for microprocessor "Elbrus-8Ñ2" The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism The parametric optimization and the automatic tuning for digital state regulators The post-silicon validation method of standard cell libraries The technique of test generator realization for built-in self-test circuitries Trends in the implementation of processor memory description and analyzers for software verification
U
	Use of parallel computing in VLSI computer-aided design
V
	VLSI microprocessor monitoring unit Variable-length code packing IP-core Virtualizing IO devices
W
	Wireless Power Transfer Appliance with High Resistance to Inductive Coils Displacements for Powering Implanted Medical Devices
6
	64-bit superscalar embedded RISC microprocessor