| Block FIR filter implementation with a data-flow recurrent signal processor |
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| Authors |
| | Khilko D.V. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-4-163-170 |
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| Abstract |
| | The article covers aspects of the prototype approbation of a data-flow recurrent signal processor in the subject area of digital signal processing. A brief description of the scientific and practical results obtained during the development of the considered prototype is presented. A set of BDTIMark2000 benchmarks is selected to assess the prototype performance. The successful testing of the most impactful DSP algorithm - FFT with point-in-place implementation through the introduction of hardware support is especially noted. The next essential algorithm for testing the prototype was a filter with a finite impulse response. The first attempt to implement a block FIR filter showed a high level of performance of the covered prototype.
However, the redundancy of the data-flow program turned out to be too high. Therefore, software and hardware optimi-zation techniques for FIR filters implementation have been analyzed. Based on the analysis results, the main directions for improving the prototype of the recurrent signal processor have been determined. Following techniques have been considered: cyclic addressing mechanisms; hardware support for cycles; optimal memory placement of samples and coeffi-cients; superscalar calculations; parallel and block imple-mentation of the filter; optimization of the multiplier microarchitecture; representation of coefficients in signed-powers-of-two form for implementation without multipliers; distributed arithmetic; multiple constant multiplications.
Applicability analysis of the studied techniques for a proto-type of a recurrent signal processor is covered. It concluded that most of the techniques could be used to improve the FFT hardware support. This hardware has been successfully re-fined and used to implement the FIR filter. The resulting solution reduced the redundancy of the block FIR filter data-flow program by almost 80% and increased the loading speed of the input signal samples.
In conclusion, unresolved problems with the implementation of other types of FIR filters, such as single-sample FIR and complex block FIR are considered. It is shown that the developed tools were designed with the goal of further devel-opment and can be efficiently modified for the effective im-plementation of these filters. |
| Keywords |
| | data-flow architecture, recurrence, digital signal processing, digital filters, FIR filters, FFT. |
| Library reference |
| | Khilko D.V. Block FIR filter implementation with a data-flow recurrent signal processor // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 4. P. 163-170. doi:10.31114/2078-7707-2022-4-163-170 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D085.pdf |
