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Resource-aware Patch Generation of Boolean Circuits
Authors
	Zhukov V.V.
	Vysotsky L.I.
	Shupletsov M.S.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-1-30-37
Abstract
	In a modern design flow, if some functionality has to be changed or functional bugs are found at late stages, restarting the whole design flow is impractical. To save time and cost, automating Engineering Change Orders (ECOs) is more practical. The idea of this approach lies in careful analysis of already synthesized circuit and generation of a patch circuit, which allows for rectification of all logical errors and functionality changes. Thus, there is no need in the repetition of already accomplished design flow steps of logical and physical synthesis. The key aspect of this approach is development of algorithms for optimized patch generation. The key parameters of the patch are its size (the number of gates), number of primary inputs and effort required for patch integration. The latter is a hard parameter to formalize, since several parameters of the synthesized circuit should be considered (e.g. resource limits imposed by the structure of the circuit). Consequently, development of algorithms for resource-aware patch generation starts to play an important role in modern ECO research.
Keywords
	Boolean circuits, logic synthesis, engineering change order, partitioning, equivalence checking, functional correction, engineering change order, Boolean matching.
Library reference
	Zhukov V.V., Vysotsky L.I., Shupletsov M.S. Resource-aware Patch Generation of Boolean Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 30-37. doi:10.31114/2078-7707-2018-1-30-37
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D065.pdf