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Hardening Self-Timed Circuit Indication against Soft Errors
Authors
	Stepchenkov Yu.A.
	Diachenko Yu.G.
	Rozhdestvenskij Yu.V.
	Morozov N.V.
	Stepchenkov D.Yu.
	Djachenko D.Yu.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-2-66-72
Abstract
	Adverse external influences (nuclear particles, cosmic rays, electromagnetic impulses) and internal disturbances (interference from adjacent signal traces, noises on power buses, and substrate) give rise to long-term (memory bit upset) and short-term (soft error) effects that affect digital circuit performance. Clock frequency rising increases the likelihood of writing soft error to synchronous register and makes synchronous circuits more sensitive to soft errors. An alternative to synchronous circuits are the self-timed ones. They are more immune to the soft errors due to dual-rail data coding and switching completion indication ensuring handshaking between their parts. The self-timed circuit's indication sub-circuit occupies 25% through 50% of the entire self-timed circuit's hardware and layout area. So, short-term soft errors, caused by ionization events and interference inductions, appear in the indication subcircuit with a probability comparable to the soft error appearance probability in the self-timed circuit rest part. Indication subcircuit soft error tolerance depends on its immunity to soft errors in the indicated self-timed circuit and failure protection of Muller's C-element that is an indication base component. XOR and XNOR cells at the indication subcircuit first stage mask so-called anti-spacer state that is one-third part of the soft errors appeared in indicated circuits. Dual interlocked C-element implementation increases the indication subcircuit failure tolerance, but not sufficiently. The article proposes to replace the two-transistor converter in the dual interlocked C-element with a four-transistor converter and to use C-elements with in-phase inputs and output for building an indication “tree” combining all partial indication signals into a total one. Together with the XOR cell at the indication subcircuit first stage, the proposed approach provides an absolute protection against both soft errors in indication subcircuit and anti-spacer in the indicated self-timed circuit.
Keywords
	self-timed circuits, failure tolerance, short-term soft error, indication, C-element, DICE-like approach.
Library reference
	Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Hardening Self-Timed Circuit Indication against Soft Errors // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 66-72. doi:10.31114/2078-7707-2020-2-66-72
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D047.pdf