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Schematic-topological design of VLSI cells
Authors
	Baranov A.A.
	Safyannikov N.M.
Date of publication
	2016
Abstract
	Variants of standard VLSI cells design on schematic level with orientation on topological level are considered. Original solutions of two-latch double edge triggered flip-flop circuit flip-flop and half adder are suggested for CAD libraries. Master-master two-latch double edge triggered flip-flop circuit distinguishes by its structure regularity and half adder by its noise stability. Workflow description and simulation data this cells are demonstrated. Topology of this flip-flop has been designed. Design of high-level systems depend on a low level cells characteristics. So generation of a cells library is one of the most important tasks while solving a problem related to perspective microelectronic systems development. It is confirmed by a recent increase of patents in the area of cells development, i.e. in classes G06F 7, G11C 7, H03K 3 of International Classifier. Increasing the number of solutions is connected not only with functional level, but also schematic level with orientation on topological level, so-called schematic-topological design. So design of new original libraries of VLSI cells are of greater scientific and practical importance. Schematic-topological achievements in creating the original cells can give a great effect in the design of digital VLSI and can significantly affect microelectronic systems characteristics, as well as can assist in the solution of problems related to the protection of intellectual property.
Keywords
	library of VLSI cells, Master-Master flip-flop, half adder, schematic-topological design, CAD.
Library reference
	Baranov A.A., Safyannikov N.M. Schematic-topological design of VLSI cells // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 220-225.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D151.pdf