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Design of Power Efficient 14-port Register File and Translation Lookaside Buffer in 28-nm Process
Authors
	Kirichenko P.G.
	Solovyeva L.A.
	Tarasov I.V.
Date of publication
	2016
Abstract
	A translation lookaside buffer (TLB) and a register file (RF) blocks are used intensively in a microprocessor core. For our 28-nm chip they were designed by a full-custom approach using same techniques and methods for both blocks as often as possible. The TLB has 64 words with a CAM part of 47 bits including 8 mask bits and a RAM part of 60 bits. The register file with 8 read and 6 write ports has 32 words of 72 bits each. Previously we designed RF with a less number of ports and bits and TLB blocks in 0.18-um and 65-nm process. However, we did not borrow completely methods and circuits used in those units due to the low power requirements. 28-nm process uses low Vdd values and has relatively high leakage current. This may lead to a significant CAM cell matchline stability reduction. To avoid signal to noise margin decreasing we implemented CAM register on cells with static CAM port instead of dynamic one. The circuit and layout design became more sophisticated but shew much more noise immunity and less leakage current value unlike the predecessors. To improve read stability in memory array we decided to divide read bitline of RF and TLB on 2 parts: a local bitline, which joins 8 bitcells and a global one. This also allowed to keep bitcell area as small as possible and to decrease leakage current. Readmerge cells (the same for RF and TLB blocks) were upgraded to reduce leakage in bus keeper module. Modification of read data register’s set-dominant latch circuit, also the same for both RF and TLB, dramatically improve its noise immunity. We simulated blocks in all 45 PVT corners to ensure their robustness. The previous designs of TLB used very simple circuitry of local read bitline precharge control. All precharge lines were deactivating during read cycle. The method has a risk of false data reading due to noise and crosstalk if one take into account low Vdd voltage and high leakage current value in 28-nm process. To ensure read stability we developed a precharge control circuit with read address or activated matchline number awareness. This circuit allows precharge deactivation on local bitlines, which should be used for reading only. As far as we used full-custom approach we could introduced High-Vt transistors on non-critical path parts of circuits. This gave us additional power savings. The results are presented in Table 1. The old precharge control circuit is designated as “PCH_ALL” and “NO_HVT” means absence of High-Vt transistors in non-critical path. One can see the leakage current reduction up to 35% and active current reduction up to 12.7% Òable 1 Active and leakage current Current PCH_ALL, NO_HVT NO_HVT Result IRF_active, mÀ - 25.82 22.91 IRF_leak, mÀ - 7.84 6.64 ITLB_active, mÀ 48.99 48.50 47.52 ITLB_leak, mÀ 5.70 6.39 4.22
Keywords
	register file, translation lookaside buffer, power consumption, leakage current
Library reference
	Kirichenko P.G., Solovyeva L.A., Tarasov I.V. Design of Power Efficient 14-port Register File and Translation Lookaside Buffer in 28-nm Process // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 129-135.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D001.pdf