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Fast Multipliers for Hardware Implementation of Artificial Neural Networks  

Authors
 Mironov S.E.
 Bureneva O.I.
 Zibarev K.M.
Date of publication
 2022
DOI
 10.31114/2078-7707-2022-4-109-116

Abstract
 The article is devoted to the structural, circuit and layout design of matrix multipliers, taking into account the peculiarities of their functioning in artificial neural networks. Taking into account the specifics of calculations performed by multipliers makes it possible to reduce their delay and area on a chip.
Purpose. Development and research of high-speed equipment for performing the multiplication operation for artificial neural networks.
Methods. Ensuring high performance and reducing hardware costs achieved by using the method of grouping multiplier digits. The layout was develop in a technologically invariant concept using original software tools based on combinatorial transistor placement methods and layout compaction methods.
Results. An analysis of the features of artificial neural networks functioning made it possible to propose the imple-mentation of a matrix multiplier with a grouping of more than two digits of the multiplier (in contrast to traditional multiplication options). The proposed implementation option can also be use in filtering problems.
Discussion. The structure and scheme of a matrix multi-plier with grouping of the multiplier bits are describe. The problem of the efficiency of multiplier cells layout designing with a grouping of a large number of multiplier bits is dis-cussed.
Keywords
 neural networks elements, neural networks hardware implementation, matrix multipliers, multiplication by a group of digits, Booth's algorithm.
Library reference
 Mironov S.E., Bureneva O.I., Zibarev K.M. Fast Multipliers for Hardware Implementation of Artificial Neural Networks // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 4. P. 109-116. doi:10.31114/2078-7707-2022-4-109-116
URL of paper
 http://www.mes-conference.ru/data/year2022/pdf/D084.pdf

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