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Random Test Generator for Multicore Microprocessor Cache Coherence Verification (Ristretto)
Authors
	Smirnov A.V.
	Chibisov P.A.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-2-31-38
Abstract
	modern system-on-chip designs contain multiple computational cores with several levels of caches, as well as a sophisticated memory subsystem. Functional verification of multi-core microprocessor models is known to be a big challenge. There are different approaches for memory subsystem and cache coherence controllers verification but an automated functional test generation strategy is the most commonly used in the industry. In this paper, the technique of automated multi-core test generation is proposed. It can be applied for cache coherence and memory subsystem check in a top-level multi-core RTL-model simulation. Moreover, the presented test generator can be very effective in generating test scenarios for FPGA-prototypes of SoC being designed. In this paper we also give a detailed description of the random test generator itself and capabilities of generated test cases. The proposed test generator got its name “ristretto” due to the similarity of the word “ristretto” with the abbreviation formed from the words “random instruction sequence” (RIS), and the word “threads” (and because ristretto is so concentrated and intense). Some self-checking validation approaches are suggested to obtain correct responses in FPGA-based verification (post-silicon validation). In the paper we also discuss bug-masking problem in post-silicon random instruction tests that arises due to limited observability.
Keywords
	multicore microprocessor, pseudorandom tests generation, functional verification, RTL-model, cache coherence, false sharing, memory subsystem, post-silicon validation, self-checking, bug masking.
Library reference
	Smirnov A.V., Chibisov P.A. Random Test Generator for Multicore Microprocessor Cache Coherence Verification (Ristretto) // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 31-38. doi:10.31114/2078-7707-2018-2-31-38
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D053.pdf