| Electrostatic Discharge Exposure on the Transistor in Consideration of Seat Capacitance |
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| Authors |
| | Drozdova A.A. |
| | Nikolaev I.I. |
| | Komnatnov M.E. |
| Date of publication |
| | 2022 |
| DOI |
| | 10.31114/2078-7707-2022-2-47-52 |
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| Abstract |
| | This paper investigates the exposure of electrostatic discharge (ESD) on power transistors located on a printed circuit board (PCB) when the capacitance of the seat and solder layers are taken into account. To surface-mount the field-effect transistors IRFZ46N and IRF4905SPbF, we developed quasi-static models for mounting seats of TO-220 and TO-263 sizes, respectively. The capacitances of the seats were calculated with and without taking into account the solder layer on the transistor electrodes. Based on the calculated capacitances, we also developed a circuit diagram of ESD exposure on the transistor. The results are presented with and without taking into account the seat capacitance. The capacitance of the seat with a solder layer was shown to affect the value of the breakdown voltage of the gate dielectric when the transistor is exposed to ESD. It was found that the critical voltage levels for the IRFZ46N and IRF4905SPbF transistors to perform well are 3 and 3.5 kV, at which the gate dielectric breakdown occurs. The difference between the simulation and experimental results was no more than 2%. |
| Keywords |
| | electromagnetic compatibility, electrostatic discharge, electronic components, transistor, breakdown voltage. |
| Library reference |
| | Drozdova A.A., Nikolaev I.I., Komnatnov M.E. Electrostatic Discharge Exposure on the Transistor in Consideration of Seat Capacitance // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 2. P. 47-52. doi:10.31114/2078-7707-2022-2-47-52 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2022/pdf/D019.pdf |
