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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 to 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 year

All topics ADC design problems Cellular automata Design of System-on-chip (SoC) and IP-blocks Design of VLSI elements Design of VLSI signal processors Design of analog and mixed functional blocks of VLSI Design of digital functional blocks of VLSI Design of fault-tolerance systems Design of micro-electromechanical systems Design of nanoelectronic devices Design of nanoelectronic devices based on Josephson junctions Design of photodetecting VLSI Design of radiation-resistant VLSI Design of technological processes Designing components for aerospace and navigation technology Genetic algorithms in VLSI CAD Methods and algorithms for automated layout design Methods for high-level simulation Methods of device technology simulation of VLSI Methods of digital information processing and digital filters Methods of electro-thermal simulation Methods of logic synthesis and functional logic simulation ... Methods of simulation of VLSI electrical characteristics Models of devices for circuit simulation Neural networks Problems of development of sensory microcircuitry Simulation of data transfer channels Study of the magnetic properties of materials Unconventional computing systems Web-based VLSI CAD design of memory cells

Selection on topic: Methods of logic synthesis and functional logic simulation in VLSI CAD

Selected papers: from 2005 to 2024 year

In selection - 104 papers

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D

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H

I

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M

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2

A
	ASPECT – a Subsystem of Event Analysis of Self-Timed Circuits Accelerated characterization technique for multi-bit flip-flops with accuracy control Algebraic Decomposition Models for Digital System Design Debugging by Simulation Algebraic Decompositions of Cofactors in BDD Representations of a Systems of Incompletely Defined Boolean Functions Algorithmic Design of Digital Operational Units with Low Power Consumption An Algorithm of Building Fast Hash Functions Based on Replacement of Symbols Analysis of Iterative Methods for Solving Logical Equation Systems and their Use in Digital System Simulation Analytical Timing Driven Global Placement of Structured ASIC A parallel critical path algorithm with loop detection for static timing analysis of sequential circuits Application of standard cell characterization results in statistical timing analysis Applying SAT Solvers and ROBDDs for Deriving Circuits Masking Logical Faults and TSs in Discrete Systems
B
	Boolean complement to modular sum codes for the concurrent error-detection systems synthesis for combinational devices of automation and computer technology
C
	CMOS circuit interval static timing analysis accounting for logic correlations Characterization of FPGA-based Digital Libraries Characterization of pseudodynamic elements Complex platform of functional verification of Mentor Graphics Computer-aided design of topology of functional blocks of custom digital VLSI Conditional jump re-alternation Limiting based speed-up of Directed Automated program testing
D
	Decompilation of Flat CMOS Circuits in SPICE Format Decomposition and Minimization of Binary Decision Diagrams for Systems of Specified Boolean Functions Decomposition of Boolean Functions for BDD Decomposition on the basis of universal systems of functions and its application at logic and topological VLSI synthesis Definition of competence areas of synthesis algorithms of combinational logic circuits Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors Delay noise analysis, using graph of constraint pairs Deriving Low Power Robust PDFs Based on Applying SAT-Solvers and Operations on ROBDDs Designing of regular circuits with consecutive connections of transistors Designing on FPGA of high-speed finite state machines Development Principles of Debugging Tools for Recurrent-Computing Device Development of Methods for Genetic Synthesis of Fault-Tolerant Logic circuits Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits Development of Special Logic Element Models for Timing Analysis of Reconfigurable System-on-a-Chip Distributed system and switching circuits optimization methods for Boolean functions of small number of variables
E
	Estimating of the Power Consumption of Combinational CMOS Circuits Based on Logic VHDL Simulation Experimental Research of Effectiveness of Programs for Minimizing BDD Representations of Boolean Function Systems in Synthesis of Combinatorial CMOS Circuits
F
	FPGA reverse engineering by model-driven development Features of processing and transmitting information in computing devices Finite state machine state splitting for power minimization Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs Formation of the reduced logical elements library for FPGA Function test set formation for design correctness checking
G
	Generation of Logical Function Libraries Generation of large sets of logical functions for digital integrated circuits CAD systems
H
	Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words High level model based verification of digital circuits behavior
I
	Integration of logic synthesis with a binding to library on the basis of universal systems of functions and direct methods of the generalized decomposition Integration of logic synthesis with binding to library in system Integro Investigation of the possibilities of practical application of the adiabatic logic to reduce power consumption of VLSI
L
	Latency Analysis in Microarchitectural Models of Communication Fabrics Linear Synthesis of k-valued Digital Structures: Principle of Generalization Linear synthesis - a new approach to the logical design of k-valued digital structures Logic Resynthesis Method in the FPGA Design Flow Logical timing analysis of digital IC reliability with NBTI and HCI degradation effects Low-Power Synthesis of Logical CMOS Circuits Low Power Driven Optimization of Two-Level Logic Circuits Low power FSM’s synthesis based on combined structural model
M
	Mathematical model of the functioning a specialized microprocessor device as a basis for compiling its functional specification Method for Binary and Vector Polynomial Expansion of Boolean Functions Method of optimum curtailing of the scheme. The effective approach for the qualitative solution for non-polynomial combinatory problems of the large and superlarge dimensions in automated designing microelectronic devices Methods of statistical timing analysis of digital circuits
N
	Noise analysis of digital circuits with accounting of logic constraints
O
	On-chip Standard Cell Delay Verification Techniques On complexity of inverter graphs for Boolean functions of small number of variables On mathematical models of digital microelectronic systems and verification of the sequence of functions performed at the design stage Optimizational transformations of VHDL-models of digital systems Ortogonalization of the DNF System of Boolean Function
P
	Partitioning methods for Large-Scale Equivalence Checking and Function Correction Principles of Constructing a System of Logic Simulation with Consideration of Destabilizing Factors Principles of construction of specialized calculators based on residual arithmetics
R
	Reliability-Driven Logic Synthesis Using Arbitrary Standard Cell Library Resource-aware Patch Generation of Boolean Circuits Reverse Engineering of VLSI for Equipment Safety Running OS Linux as a stage of functional testing of microprocessors
S
	Scalable diode macromodel with high modeling accuracy Self-checking digital devices organization by Boolean complement method with Hamming codes SoC focused technologies of brain-like quantum computing SsVER - system of synthesis and verification of combinational logic schemes Static timing analysis aware false conduct path detection in terms of logic implication Statistical timing analysis aware of reconvergence of conduction paths and transition variations Subsystem of CAD for synthesis of the encoder/decoder IP-cores for convolution turbo codes
T
	Test automation tool for the computing unit of the recurrent operational level Testing Systems with Behavior Parallelism Based on a Reduced Reachability Graph The Functional Method of the Analysis of Speed-Independent Circuits of Any Size The Gate Delay Analysis Method Accounting for Simultaneous Input Switching The Optimal Algorithm for Generating a Complete Test for Checking the Simplest Single Logical-Dynamic Faults for an N-Input Combinational Device The algorithm for synthesis of digital ICs based on the Gilbert decomposition The features of automated design of derangements generators The method of peak current estimation at logic level taking into account simultaneous switching of inputs The method of static power reducing for CMOS circuits based on sleep transistors with operation speed control The methods of time-logic analysis of library elements and VLSI blocks for advanced technologies with a vertical transistor’s gate The system of logical optimization of functional structural descriptions of digital circuits based on production-frame knowledge representation model The use of VHDL models of partial Boolean functions for the design of digital circuits The way design for testability of logical transformers Three level logic minimization using graphics processing units Timing analysis of digital circuits basing on logic correlations
U
	Use of parallel computing in VLSI computer-aided design Using clusterization in logical synthesis
V
	VHDL-Simulation-Based Evaluation of CMOS-Circuits Power Consumption Verification of Logical Descriptions of Combinational Circuits Verification of digital devices with concurrency behavior
W
	Web-based Characterization of Digital Libraries Web-based Generation of Highlevel Models of Digital Cells Web-based automatic generation of input patterns at characterization of digital cells
2
	28nm IC’s Parameters Optimization without RTL Changing