| Applying SAT Solvers and ROBDDs for Deriving Circuits Masking Logical Faults and TSs in Discrete Systems |
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| Authors |
| | Matrosova A.Yu. |
| | Provkin V.A. |
| | Ostanin S.A. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-2-35-42 |
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| Abstract |
| | A combinational circuit Ρ (the combinational part of a sequential circuit) consisting of gates and its sub-circuit Cs with a set V of output nodes and a set U of input nodes are considered. A set V comprises outputs of circuit C fault gates (logical faults are regarded) and inputs of fault free gates so that these inputs are at the same time outputs of lines in that of which Trojan Circuit (TC) may be injected. A set U consists of either internal nodes of circuit C or some its input nodes. Correction of circuit C behavior in the frame of Engineering Change Order (ECO) technology is suggested. It is reduced to deriving masking circuit (patch circuit Cp) that is simpler Cs. Note that it is necessary additional area for Cp and we try to decrease it. There are many ways of deriving masking circuits. As a rule, the approaches are based on results of circuit C simulation on sub-set of its input vectors. These approaches guarantee correct behavior on these input vectors. We derive masking (patch) circuit using incompletely specified functions of nodes from V. This way guarantees a correct behavior of circuit C on all input vectors. We form incompletely specified Boolean functions for each node v from V depending on either internal variables (a set U) or some input variables of circuit C. Deriving of incompletely specified Boolean functions is based on either applying operations on ROBDDs or/and using SAT solvers. The situation when faults are detected on the last stage of a circuit fabrication is considered. In this case we need to return to the first stages of the fabrication or refuse applying this circuit at all. To increase yield masking faults is used. In this case incompletely specified Boolean functions of fault nodes, as a rule, are poor determined ones. In this paper we consider TCs that pay load is injected into circuit C line. Output of this line that is input of fault free gate usually is also characterized by poor determined incompletely specified Boolean function. That is why applying information about these functions we may get simpler Cp in comparison with Cs. Experimental results represented in paper [5] confirms that. Having got incompletely specified Boolean functions we get masking circuit applying ESPRESSO and ABC systems. Note that SAT solvers become more and more effective and operations on ROBDDs are characterized by polynomial complexity. We hope that applying of both techniques we may execute masking more and more complicated circuits. |
| Keywords |
| | combinational circuits, incompletely specified Boolean functions, observability functions, Disjoint Sum of Products (DSoP), Tseitin CNF, ROBDDs, SAT solvers, ECO technologies |
| Library reference |
| | Matrosova A.Yu., Provkin V.A., Ostanin S.A. Applying SAT Solvers and ROBDDs for Deriving Circuits Masking Logical Faults and TSs in Discrete Systems // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 35-42. doi:10.31114/2078-7707-2020-2-35-42 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D022.pdf |
