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Deriving Low Power Robust PDFs Based on Applying SAT-Solvers and Operations on ROBDDs
Authors
	Matrosova A.Yu.
	Tychinskiy V.Z.
	Andreeva V.V.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-2-43-49
Abstract
	new approach to deriving low power test sequences that detect robust testable PDFs in logical circuits is suggested. Decreasing power consumption is provided by decreasing the number of switches during testing and by reducing length of the test sequence. The approach is based on finding all test pairs consisting of neighbor Boolean vectors for a circuit path. The test pairs are compactly represented by the proper ROBDD [2]. Each pair of neighbor Boolean vectors generates three neighbor Boolean vectors that detect robust PDFs of both rising and falling transitions of a path. Current approaches are oriented to finding if only one test pair both for rising and falling transition of a circuit path there exists. Applying all test pairs of neighbor Boolean vectors and using properties of ROBDDs representing these pairs we provide addition facility to cut power consumption of the test sequences. The general principles of deriving the test sequences are based on intersection of ROBDDS of different paths [4] and a procedure [4] oriented to cutting Hemming distance between neighbor vectors of different ROBDDs. Some experimental results for the longest circuit paths are represented. They demonstrate the high quality of test sequences in terms of power consumption, not achievable by traditional methods. In the case where the use of ROBDDs is difficult due to their large sizes, an alternative approach is proposed, which is based on the obtaining of the Tseitin CNF [5]. The complexity of this CNF deriving linearly depends on the number of gates in the circuit. The obtained CNF is fed to the input of the SAT solver, which allows getting one, several or all test pairs for the selected path. Thus, when testing circuits, it becomes possible to find the proper ratio between the power consumption of the test sequence and the time taken to obtain it.
Keywords
	robust testable Path-Delay Faults (PDFs), reduced ordered binary decision diagrams (ROBDD), SAT solvers, combinational circuits, sequential circuits.
Library reference
	Matrosova A.Yu., Tychinskiy V.Z., Andreeva V.V. Deriving Low Power Robust PDFs Based on Applying SAT-Solvers and Operations on ROBDDs // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 43-49. doi:10.31114/2078-7707-2020-2-43-49
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D025.pdf