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Subsystem of CAD for synthesis of the encoder/decoder IP-cores for convolution turbo codes
Authors
	Bychkov N.A.
	Kovalev A.V.
Date of publication
	2010
Abstract
	A software TurboGen has been worked out. It is defined as a subsystem of CAD for synthesis of VHDL specifications of the IP-cores of the convolution turbo codes encoder/decoder. A new structure of the turbo code computing system is highly fast acting for account of a pipelined me-thod in the designing along with an effective application of the core memory banks has been sug-gested. A particular emphasis is placed on the hardware support of a maximum a posteriori proba-bility algorithm (MAP) of the turbo coding device. The analyses of the logical synthesis results fur-thered to define and estimate the hardware expenditure, required for VLSI realization of the complex functional units of the convolution turbo codes encoder/decoder, and confirm the rationality of VLSI computing resources application.
Keywords
	CAD, IP-core, convolution turbo code, encoder, decoder, MAP algorithm, VLSI, FPGA, VHDL.
Library reference
	Bychkov N.A., Kovalev A.V. Subsystem of CAD for synthesis of the encoder/decoder IP-cores for convolution turbo codes // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 20-25.
URL of paper
	http://www.mes-conference.ru/data/year2010/papers/m10-117-58341.pdf