| Low Power Driven Optimization of Two-Level Logic Circuits |
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| Authors |
| | Cheremisinova L.D. |
| | Cheremisinov D.I. |
| Date of publication |
| | 2010 |
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| Abstract |
| | The problem of low-power design of two-level AND-OR CMOS circuits is considered. The package of methods and programs is supposed that provides minimization of Boolean functions in disjunctive normal form (DNF) according to complexity and power dissipation. Realized methods of Boolean functions minimization are extensions of known
methods by adding heuristics that turn the DNF minimization process towards lowering the power dissipation in the sough circuit. The estimations of power consumption, which are used during two-level circuit optimization and ensure power consumption lowering, and the results of
computer experiments are given. |
| Keywords |
| | logical design; minimization of Boolean functions; power consumption |
| Library reference |
| | Cheremisinova L.D., Cheremisinov D.I. Low Power Driven Optimization of Two-Level Logic Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 14-19. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-54-80751.pdf |
