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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 to 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 year

All topics ADC design problems Cellular automata Design of System-on-chip (SoC) and IP-blocks Design of VLSI elements Design of VLSI signal processors Design of analog and mixed functional blocks of VLSI Design of digital functional blocks of VLSI Design of fault-tolerance systems Design of micro-electromechanical systems Design of nanoelectronic devices Design of nanoelectronic devices based on Josephson junctions Design of photodetecting VLSI Design of radiation-resistant VLSI Design of technological processes Designing components for aerospace and navigation technology Genetic algorithms in VLSI CAD Methods and algorithms for automated layout design Methods for high-level simulation Methods of device technology simulation of VLSI Methods of digital information processing and digital filters Methods of electro-thermal simulation Methods of logic synthesis and functional logic simulation ... Methods of simulation of VLSI electrical characteristics Models of devices for circuit simulation Neural networks Problems of development of sensory microcircuitry Simulation of data transfer channels Study of the magnetic properties of materials Unconventional computing systems Web-based VLSI CAD design of memory cells

Selection on topic: Methods and algorithms for automated layout design

Selected papers: from 2005 to 2024 year

In selection - 101 papers

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C

D

E

F

G

H

I

L

M

N

O

P

R

S

T

V

Y

3

A
	A Method of Multi-level Uniform Grids for Spatial Searching A Parasitic Resistance Extraction Method for Early Analysis of Complex Shaped Power Delivery Networks About duplication of elements at VLSI layout Adaptation in Problems of VLSI Topology Designing Adaptive procedure of choice of modules orientation at VLSI planning A global router for nanometer standard cells Algorithm for Constructing Voronoi Diagram of Orthogonal Polygons in Linf-metric Algorithm for design rule violation clean-up after physical design Algorithm of Inter-gate Resynthesis at the Transistor Level for Computer-aided Design of Microelectronic Circuits Algorithms for dynamic all-pairs shortest path problem Algorithms of evolutionary swarm intelligence for solving graph partition problem Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component Analytical Timing Driven Global Placement of Structured ASIC An extensible framework for developing and testing of the layout processing algorithms A physical synthesis to islands of cells with the same diffusion width Application of SAT Approach to Switch Blocks Routing for Reconfigurable System-on-a-chip Application of dynamic Voronoy diagrams to design rule checking A stick-diagram based standard cell layout synthesis tool Automatic Determining of Auxiliary Constraints at Boundaries for Standard Cells Synthesis Flow Automatic layout synthesis of standard cell layouts based on re-using existing transistor placement patterns and routing patterns
B
	Bioinspired VLSI chip planning methods Bioinspired VLSI chip planning methods
C
	CELLERITY: THE SYSTEM OF AUTOMATIC SYNTHESIS OF STANDARD CELL LAYOUT Choice of optimum connections in a tree in view of Elmore delays Co-evolution VLSI partitioning algorithm Cognitive Contradiction’s Visualization for VLSI Layout Decomposition for Double Patterning Issues Comparative Analysis of Clustering and Placement Methods for Reconfigurable System-on-Chips Comparative analysis of the memory elements and sense amplifiers for high-temperature VLSI RAM Complex algorithm of switch box routing Complex parameterization technology for topological projects of regular VLSI macroblocks Computer-aided design of topology of functional blocks of custom digital VLSI Configuration of microelectronic means on the basis of iterative clusterization taking into account time delays Constraint Driven VLSI Floorplanning by Non-Linear Optimization Converting VLSI macroblock structure by regrouping uniform function blocks
D
	DFM Improvement of Hierarchical Layouts Decomposition Algorithm of the Electronic Circuits with Elements with Varied Area Design a functional model of FPGA whith single-driver technology in Xilinx ISE system Determination and comparison of M-factor for devices with the type defined by the user (GENERIC) Development and Comparative Analysis of Initial Placement Methods for FPGA Development of algorithm of three-dimensional layout of VLSI on the basis of iterative clusterization Distribution of connections by layers in multi-layer global routing
E
	Electromigration Tolerance Improvement in Standard Cells Evolutionary routing in the channel on the basis of symbolical representations
F
	Flip Chip package design for sophisticated ASIC under small lot production
G
	Gate nets routing in nanometer standard cells with ports placement Generation of Initial Partitions for Hypergraph Balanced Cut Problem Genetic search at construction of connecting trees at a design stage of VLSI layout Global placement algorithm for structured ASIC Global routing accounting time restrictions and route-making resources
H
	Heuristics of netless final layout of unrouted nets in the commutational block Hybrid Bioinspired Algorithm for Forming Standard Cell Lines in the Design of the VLSI Topology
I
	IR voltage drop and Electromigration Aware Wire Sizing Algorithm Improving the efficiency of the design integrated circuits on FPGA with limited resources to trace Initial placement of digital logic cells in integrated circuits considering net priority
L
	Layout Dependent Effects Impact on Standard Cells Layout in 28 nm Technology Node Layout of microelectronic means on the basis of the multilevel approach
M
	MSV-driven VLSI floorplanning Method of construction of restrictions for an expanded set of technological rules Method of placement blocks of three dimensional integration IC Methods for speeding up the modified Pathfinder routing algorithm for island-style FPGA Methods of designing custom IP-blocks based on the elements with regular topological structure in layers of polysilicon and diffusion Minimization of undesired layout patterns during standard cell synthesis Multi-layer global routing by a method of collective adaptation
N
	Non-linear optimization framework for cell placement legalization
O
	Optimization for some phase of Komdiv64-RIO design flow Optimization of Capacitor Based DAC Optimization of TSMC 28nm Physical and Logical VLSI Design Flow Optimization of VLSI Regular Power Grid Optimization of a Modal Filter on a Double-Sided PCB with Broad Side and Edge Coupling
P
	Parallel VLSI Layout Decomposition Algorithm for Double Patterning Placement of Logic Cells of Integrated Circuits with Simultaneous Consideration of Performance and Thermal Mode Placement of VLSI Elements Based on Swarm Intelligence Models Polygons size and form optimization in layout compaction process Population VLSI Planning Algorithm by the Method of Crystallization of alternatives field Probabilistic approximation of a location problem Problem of a transistor length variation in a standard cell at multi-objective optimization of nano-size VLSI Procedures of Channel Rooting on the Basis of Hybridization of Swarm Intelligence with Genetic Search
R
	Representation of the Matrix Architecture in the Form of a Working Field in the Problem of the Initial Placement of VLSI Components Results of computer modelling of the decision of a problem of placing of elements VLSI taking into account time delays Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints
S
	Schematic-topological design of VLSI cells Shortest trees construction on the basis alternatives field crystallization method Speeding up the evaluation of polygons mutual placement task for double pattern technology Splitting on the basis of multilevel parallel evolutionary adaptation Standard Cell Routing via Boolean Satisfiability Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip Synthesis of memory units using a description of design rules via Boolean functions of layout objects Synthesis of topology of standard CMOS cells taking into account effect of electromigration System of Compaction and Migration of Standard Cell Layouts
T
	The Hierarchical Approach to Island Style Reconfigurable System-on-a-chip Routing The Problem of Element Placement on a Printed Circuit Board: the Solution Based on a Simplified Model of a Microstrip Line The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs The advanced algorithms of comparison of graphs of electric circuits The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory Timing-driven placement algorithm based on delay matrix model for reconfigurable system-on-chip Topological Graph Drawings Transistor placement at standard cell level Two-level evolutional-genetic routing of electric circuits on graph models
V
	Voronoi diagram based graph models building in VLSI physical design
Y
	Yield enhancement of standard cell layout
3
	3 design recommendations for radiation-hardened high-density SRAM cells