| Speeding up the evaluation of polygons mutual placement task for double pattern technology |
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| Authors |
| | Bulakh D.A. |
| | Korshunov A.V. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-3-41-48 |
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| Abstract |
| | Manufacturing ICs with scale less than 22 nm using optical lithography requires the use of a number of special techniques for preliminary preprocessing layout information and the most used in nowadays is double patterning technology (DPT). Implementation of this technique requires to solve main problem – how to compare all the distances between all the polygons within given layout. In this paper we propose an algorithm which aims to reduce computations and allows to detect only polygons that are in a required proximity. Funding: The reported study was funded by RFBR, project number 20-07-00556 |
| Keywords |
| | VLSI, layout, double patterning, double exposure, sparse matrices |
| Library reference |
| | Bulakh D.A., Korshunov A.V. Speeding up the evaluation of polygons mutual placement task for double pattern technology // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 41-48. doi:10.31114/2078-7707-2020-3-41-48 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D087.pdf |
