| Development of algorithm of three-dimensional layout of VLSI on the basis of iterative clusterization |
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| Authors |
| | Barinov S.V. |
| | Kurejchik V.M. |
| Date of publication |
| | 2008 |
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| Abstract |
| | In work the new technology of three-dimensional VLSI layout is proposed. It is based on the hierarchical approach, allowing to reduce time and partially to solve a problem of time delays. Time complexity of the developed algorithm is within the limits of linear and square-law dependences. |
| Keywords |
| | three-dimensional layout of VLSI, iterative clusterization |
| Library reference |
| | Barinov S.V., Kurejchik V.M. Development of algorithm of three-dimensional layout of VLSI on the basis of iterative clusterization // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2008. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2008. P. 55-60. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2008/07.pdf |
