Listing of all the works of the organization. Click on the work title to get the full information.
| 2005 | |
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Glushkov A.V., Belyaev A.A., Putrya F.M., Alekseev I.N., Mironova Yu.V.
“MULTICORE” platform IP-library of SoC peripherals
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Glushkov A.V., Solokhina T.V., Petrichkovich Ya.Ya.
Alarm controllers MS-0226 and ÌÑ-0226G on the basis of platform "MULTICORE"
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Goussev V.V., Enin S.V., Lihih S.N., Lavlinsky S.A., Menyajlov D.E., Petrichkovich Ya.Ya., Skok D.V., Solokhina T.V., Smirnova I.I., Sudnev E.N., Gerasimov Yu.M.
Analog-digital "system-on-chip" MF01 of series "Multiflex"
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Glushkov A.V., Gribov Yu.I., Silin V.A., Solokhina T.V., Gerasimov Yu.M., Nefedov V.A., Shejnin Yu.E.
Analog-digital "system on crystal" peripheral controller MCT-01 on the basis of IP-libraries of a platform "MULTICORE"
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Solokhina T.V., Petrichkovich Ya.Ya., Glushkov A.V.
Architecture of domestic IC series of type "system or network on chip" on the basis of IP-libraries of platform "MULTICORE"
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Kozlova N.N., Solokhina T.V., Gribov Yu.I., Belyaev A.A.
Configurable IP-cores architecture analysys using criterion of implementation ability in “MULTICORE” platform IP-library
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Aleksandrov Yu.N., Nikolsky V.F., Kuchinsky A.S., Chuprinov A.A., Grachev R.V., Mironova Yu.V.
Library of applied functions in structure of MCStudio™ environment for development of the software "system-on-chip" of series "MULTICORE"
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Belyaev A.A., Solokhina T.V., Glushkov A.V., Aleksandrov Yu.N., Petrichkovich Ya.Ya., Mironova Yu.V., Gerasimov Yu.M.
MCam-01 mixed signal multimedia processor
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Belyaev A.A.
Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library
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Bajkov V.D., Gerasimov Yu.M., Rogatkin Yu.B.
Peripheral analog-digital blocks for CMOS VLSI of type "system-on-chip"
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Alekseev M.N.
Route of designing "system-on-chip" on the basis of IP-libraries of a platform "MULTICORE"
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Shejnin Yu.E., Suvorova E.A., Rozhdestvenskij D.A., Solokhina T.V., Glushkov A.V., Alekseev I.N., Gerasimov Yu.M.
Route of development and FPGA-verifications of IP-core of controller SpaseWire link for "system-on-chip" on the basis of platform "MultiCore"
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Perekin R.N., Glushkov V.D., Glushkov A.V., Nikolsky V.F.
Technology of debugging "system-on-chip" of series "MULTICORE"
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Sinitsyn V.V., Kosyrev S.A., Nikolsky V.F.
The environment of development of the software for "system-on-chip" of series "MULTICORE" MCStudio_Lnx
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| 2006 | |
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Aleksandrov Yu.N., Kuchinsky A.S., Zinchenko O.N., Kolobanova E.S., Solokhina T.V.
Characteristics of the "Multicore" series controllers for FFT processing signal in real time and their application in radar
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Solokhina T.V., Glushkov A.V., Petrichkovich Ya.Ya., Grishin V.Yu., Eremeev P.M., Sirenko V.G., Shejnin Yu.E.
Family of domestic DSP-controllers "MultiCore" and elements of system interface "MultiCore-the designer" for construction of scaled parallel systems of teraflop productivity
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Glushkov A.V., Solokhina T.V., Petrichkovich Ya.Ya., Gorbachev S.V., Suvorova E.A., Shejnin Yu.E.
Multiprotocol switchboards for the heterogeneous distributed onboard complexes
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Putrya F.M.
Optimization of structure of controllers of serial buses. The solution of problems of lack of pins of a integrated circuit and loading of the processor at data transmission
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Belyaev A.A.
Pipeline structure optimization according to performance criterion for DSP-core with Harvard architecture
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Aleksandrov Yu.N., Grachev R.V., Solokhina T.V.
The block of digital operative processing ùà matrix thermovisual photoreceiver on the basis of the signal microcontroller
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| 2008 | |
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Solokhina T.V.
Architecture of DSP-accelerators on the basis of a platform "MultiCore" for supercomputers of new generation
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Chernyh A.V.
Digital sigma-delta modulator
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Gerasimov Yu.M., Glushkov A.V., Grigoryev N.G., Petrichkovich Ya.Ya., Solokhina T.V.
Features of designing of radiation-proof libraries of elements, complex-functional blocks and nano-VLSI SoC
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Putrya F.M.
Method of automation of process of development of the crossbar for multicore system whith nonuniform memory access
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Belyaev A.A., Gribov Yu.I., Solokhina T.V.
Pipelining and parallelization: two approaches to rise computational performance
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Putrya F.M.
Research, development and optimization of data exchange hardware in multicore computing systems
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Chernyh A.V.
Research and development of structural decisions of frequency synthesizers on the PLL basis
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Yanakova E.S.
The "Multicore" series processors features for signal processing in modern multifunctional radar
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Milov A.N.
The conceptual approach to construction of the device of visualization of three-dimensional images in format OpenGL on processors of a series "Multicore"
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| 2010 | |
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Putrya F.M., Medvedev I.A.
Hardware streams synchronization methods for multicore cluster
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Belyaev I.A.
Huffman encoder IP-core for JPEG image compression
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Yanakova E.S.
Methods of matched filtering radar broadband signals with minimum time delays
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Belyaev A.A.
Pipeline Depth Influence on DSP Performance
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Bajkov V.D., Gerasimov Yu.M., Kondratenko S.V., Solokhina T.V.
Special features and results of designing the family of LVDS CMOS 0,25/0,18/0,13 ìm drivers and receivers
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| 2012 | |
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Medvedev I.A.
An Efficient Router Bufferization for Network-on-Chip Design
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Lobanova A.Y.
Analysis of efficiency of complex use low-power techniques for blocks of digital VLSI
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Belyaev A.A.
Architectural features of VELCore-01 video processing core
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Belyaev I.A.
CAVLC encoder IP-core for H.264/AVC
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Yanakova E.S.
Signal Seepage Impact on the Matched Filtration Results in Radar with Continuous Emission
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Putrya F.M.
SystemVerilog object-oriented programming features for functional verification of multi-core SoC
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| 2014 | |
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Belyaev A.A., Gavrilov V.S., Kuznetsov D.A., Petrichkovich Ya.Ya., Solokhina T.V., Frolov D.S., Funkner A.A.
Evolution in the area of multicore heterogeneous video data processing systems
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Frolov D.S., Pirogov P.P., Aleksandrov Yu.N., Gribov Yu.I., Belyaev A.A.
IP-Core "ACC_Cores" as part system-on-chip. Multifunctional hardware accelerator Fast Fourier Transform - FFT_RT_Core
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Medvedev I.A., Putrya F.M.
Interconnect Verification Methods Based on Unified Test Infrastructure
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Gerasimov Yu.M., Domozhakov D.A., Kondratenko S.V., Lomakin S., Solokhina T.V.
Methods of implementation of high-speed serial channels CMOS transceivers on a physical level
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Belyaev A.A., Kolesnikova I.Y., Kuznetsov D.A.
Motion Estimation IP-core Implementation for H.264 Full HD Video Codec
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Bezglasnaya K.A., Kolbasov Y.S., Medvedev I.A., Putrya F.M.
Problems of platform approach for System on Chip and IP cores test infrastructure creation and their solutions
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Gerasimov Yu.M., Grigoryev N.G., Goussev V.V., Kobylyatskiy A.V., Petrichkovich Ya.Ya.
Radiation-hardned CMOS VLSI SRAM in bulk technology
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Golovina E., Makeeva M., Nikolaev A.V., Putrya F.M., Smirnov A.A.
Reusable complex Soc level tests creating and debugging method
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Bajkov V.D., Garmash A.A., Dubinskiy A.V.
Using the gate capacitance of MOS transistor as LPF's capacitance and its impact on the PLL's characteristics of quality
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Belyaev I.A.
Variable-length code packing IP-core
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| 2016 | |
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Poperechny P.S.
Adjustable error-correcting encoder for Systems on Chip
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Lobanova A.Y., Menshenin L.V.
Analysis of the impact of standard cells placement and power network configuration on the layout design of a microprocessor component
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Zhezlov K.A., Kolbasov Y.S., Kozlov A.O., Nikolaev A.V., Putrya F.M., Frolova S.E.
Automation of verification environments development process providing a through design flow for design, verification and research of IP-blocks and SoC
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Domozhakov D.A., Dubinskiy A.V., Rannev N.Y.
Bit error rate calculation in high performance communication channels
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Poperechny P.S.
Polynomial modular multipliers for error correcting code devices
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Gerasimov Yu.M., Grigoryev N.G., Kobylyatskiy A.V.
The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI
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| 2018 | |
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Kobylyatskiy A.V., Sergeev D.K.
On-chip Standard Cell Delay Verification Techniques
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Khokhryakov E.I.
Recovering Signal and Σ-Δ Modulator Parameters
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Garashchenko A.V., Nikolaev A.V., Putrya F.M., Sardaryan S.S.
System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture
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| 2020 | |
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Bykova A.V., Polunin M.N.
Criteria for the numerical evaluation of data recovery algorithms for analogue-information converters
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Skripnichenko M.N.
High-level model based calibration technique design for SAR ADC
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Poperechny P.S.
High-performance scheme of FFT calculation with conflict-free memory access
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Nikitin S.A., Nikolaev A.V., Putrya F.M., Neklyudov I.A.
Route automation of Functional Verification based on IP-XACT standard
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Yanakova E.S., Macharadze G.T., Kostulin N.V., Tiurin A.A.
Solving large SLE on heterogeneous SoC of «Multicore» series
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Zhezlov K.A.
The methodology of automated performance analysis of SoC interconnect subsystems, according to the SoC structure and application
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| 2021 | |
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Belyaev A.A., Belyaev I.A., Petrichkovich Ya.Ya., Poperechny P.S.
High-performance parallel BCH encoder with reconfigurable correction capability
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Zhezlov K.A., Belyaev A.A., Putrya F.M.
Implementation of Methodology of SoC Interconnects Automated Performance Analysis into the Verification Route
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Macharadze G.T.
MPI-based Software Model for Parallel Computing in Heterogeneous Clusters
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Belyaev A.A., Belyaev I.A., Petrichkovich Ya.Ya.
Parameterizable matrix multiplier of fixed-point binary numbers in direct and complementary code
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| 2022 | |
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Belyaev A.A., Shchuchkin E.Yu.
DC-DC Converter Conducted Emission Level Estimation at Design Stage
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Skripnichenko M.N.
Implementation of Area Optimal FIR Filters Based on Lookup Tables for Sigma-Delta Modulator Signal Processing
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