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Implementation of Methodology of SoC Interconnects Automated Performance Analysis into the Verification Route
Authors
	Zhezlov K.A.
	Belyaev A.A.
	Putrya F.M.
Date of publication
	2021
DOI
	10.31114/2078-7707-2021-3-39-42
Abstract
	The article discusses the problems of standalone verification and performance analysis of interconnect subsystem as a part of a SoC. There are revealed the reasons of standalone verification need. Today interconnects are the critical point of modern SoCs in terms of performance and it is worth starting verification as soon as possible. Also tests runtime for interconnect only is less than for a whole system. The problems of standalone performance analysis are the following. It is necessary to take into account the constraints imposed on the interconnect by the system, and the requirements target tasks; a methodology for describing traffic models in the is required, which is capable of describing the traffic of target applications; you need a tool for calculating performance metrics and criteria for their assessment. The paper gives a comparison of two approaches able to solve those problems. The approaches are the Cadence Interconnect Workbench tool and the automated performance analysis methodology developed by JSC SPC "ELVEES". It is discovered that Cadence IWB is capable of analyzing interconnect performance for synthetic test cases, but methodology developed in “ELVEES” has some advantages. It can describe traffic patterns more precisely (including time and data dependences between data streams) which allows you to construct test scenarios close to real usecases. That methodology also includes a complex of performance metrics and criteria which allows you to investigate performance bottlenecks. The results of the implementation of this methodology into the design route of JSC SPC "ELVEES" are also given. It can reduce 3-9 times the time spent on test environment and tests construction, and reduces the amount of bugs concerned interconnect which were discovered on further design steps.
Keywords
	SoC, performance analysis, usecase, standalone verification, performance metrics, Cadence Interconnect Workbench, System VIP.
Library reference
	Zhezlov K.A., Belyaev A.A., Putrya F.M. Implementation of Methodology of SoC Interconnects Automated Performance Analysis into the Verification Route // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 3. P. 39-42. doi:10.31114/2078-7707-2021-3-39-42
URL of paper
	http://www.mes-conference.ru/data/year2021/pdf/D040.pdf