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Adjustable error-correcting encoder for Systems on Chip
Authors
	Poperechny P.S.
Date of publication
	2016
Abstract
	Nowadays a BCH (Bose–Chaudhuri– Hocquenghem) error-correcting coding is widely used in different technical fields, such as telecommunication, data storing systems etc. To cover a lot of these demands on a System-on-Chip (SoC) two main requirements should be met: a parallelization for data bus stream and universality for different error-correcting capability. Traditional serial encoder consists of linear feedback shift register (LFSR) and switches. To overcome many error-correcting coding capabilities one SoC should have a lot of encoders with different capabilities. So, this approach suppose very large chip square. This article offers one universal decision for different requirements. Special registers store generating polynomial coefficients, and can be changed in working process. Also, the parallelization approach is offered too. This technique allows getting data from input bus. There are in-common mathematical equations for both software and hardware implementations for different data bus. The comparing results of logical hardware synthesis are presented. The proposed encoder has bigger throughput comparing with traditional approach. The universality decreases chip square consumption if using of different error-correction capabilities is needed.
Keywords
	Error-correction coding, encoder, linear feedback shift register (LFSR), SoC
Library reference
	Poperechny P.S. Adjustable error-correcting encoder for Systems on Chip // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 266-273.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D033.pdf