| High-performance parallel BCH encoder with reconfigurable correction capability |
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| Authors |
| | Belyaev A.A. |
| | Belyaev I.A. |
| | Petrichkovich Ya.Ya. |
| | Poperechny P.S. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-3-117-121 |
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| Abstract |
| | The article proposes a method for implementation of a high-performance BCH (Bose Chaudhuri Hocquenghem) encoder with parallel processing of incoming data, as well as with the possibility of reconfiguring the code correcting level capability during the operation of the device. The appropriate analytical expressions are derived for a high-performance parallel implementation of an encoder. The hardware implementation of the device is considered. The BCH codec operation simulation results for various error packet lengths are presented. |
| Keywords |
| | error-correcting codes, correcting level capability, BCH (Bose Chaudhuri Hocquenghem) encoder, linear feedback shift register (LFSR). |
| Library reference |
| | Belyaev A.A., Belyaev I.A., Petrichkovich Ya.Ya., Poperechny P.S. High-performance parallel BCH encoder with reconfigurable correction capability // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 3. P. 117-121. doi:10.31114/2078-7707-2021-3-117-121 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D067.pdf |
