Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

Themes

---

Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 to 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 year

All topics ADC design problems Cellular automata Design of System-on-chip (SoC) and IP-blocks Design of VLSI elements Design of VLSI signal processors Design of analog and mixed functional blocks of VLSI Design of digital functional blocks of VLSI Design of fault-tolerance systems Design of micro-electromechanical systems Design of nanoelectronic devices Design of nanoelectronic devices based on Josephson junctions Design of photodetecting VLSI Design of radiation-resistant VLSI Design of technological processes Designing components for aerospace and navigation technology Genetic algorithms in VLSI CAD Methods and algorithms for automated layout design Methods for high-level simulation Methods of device technology simulation of VLSI Methods of digital information processing and digital filters Methods of electro-thermal simulation Methods of logic synthesis and functional logic simulation ... Methods of simulation of VLSI electrical characteristics Models of devices for circuit simulation Neural networks Problems of development of sensory microcircuitry Simulation of data transfer channels Study of the magnetic properties of materials Unconventional computing systems Web-based VLSI CAD design of memory cells

Selection on topic: design of memory cells

Selected papers: from 2005 to 2024 year

In selection - 32 papers

A

B

C

D

F

H

I

M

N

O

P

R

S

T

3

A
	A Method for Scalable Verification of PROMELA Models of Cache Coherence Protocols Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory Analysis of Power Consumption of Matching Signals Summation Circuits for 65 nm CMOS Associative Memory Registers
B
	Built-in self-repair for SRAM with redundant elements
C
	Comparative analysis of the memory elements and sense amplifiers for high-temperature VLSI RAM
D
	Design of the hybrid CAM register
F
	Features of magnetization reversal in a MRAM cell — I. In-plane anisotropy Features of magnetization reversal in a MRAM cell — II. Perpendicular anisotropy
H
	High-speed content addressable memory block design Hybrid method of memory allocating in multibank platforms based on the DSP NeuroMatrix architecture
I
	Investigation of single event upset reliability for SOI CMOS SRAM cells using mixed-mode 3D TCAD-SPICE simulation
M
	Mathematical Model of the SOT-MRAM Cell based on the Spin Hall Effect Mechanisms of Multiple Cell Upsets in Memory Methodology of the optimization and efficiency evaluation for the Secondary Cache Model for detecting counterfeit recovered SRAM based on accelerated aging Multibank memory bandwidth analysis in on-chip system
N
	NAND Flash memory controller IP-core
O
	Optimizing the prefetch mechanism in the secondary cache memory
P
	Principles of Designing Devices for Test Diagnosing of High-speed Microchips and Semiconductor Memory
R
	Radiation hardened EEPROM structures integrated with SOI CMOS techology Random Test Generator for Multicore Microprocessor Cache Coherence Verification (Ristretto) Readout circuit from the nonvolatile memory Reliability evaluation for SEU in cache in system-on-chip design Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints
S
	Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection Software package for Technology Computer-Aided Design of spintronic devices based on magnetic tunneling junctions Statistical approach to multiple cell upsets description in highly scaled memory circuits Structure and Algorithm Development of Built-in Self-repair for SRAM Synthesis of memory units using a description of design rules via Boolean functions of layout objects
T
	The Design of Current Memory Elements Based on the Mathematical Tool of Linear Algebra The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
3
	3 design recommendations for radiation-hardened high-density SRAM cells