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Principles of Designing Devices for Test Diagnosing of High-speed Microchips and Semiconductor Memory
Authors
	Evdokimov A.P.
	Ryabtsev V.G.
	Melikov A.V.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-2-23-30
Abstract
	Article is described about applying parallelization of the formation process of forcing vectors to improve the performance of test devices for diagnosing microcircuits and memory modules. Their sequential transfer to the inputs diagnosed device is by switches. In this article, it is parallel processes of read responses. The proposed method makes it possible to increase the frequency of the test actions formation and the processing of read responses p-times, where p – is the coefficient of operation parallelization. The structure of the multiprocessor diagnostic test device consists of the interacting control and p operation processors. Each operational processor generates the address code of the diagnosed memory cell À³ and the data codes Ò³, which are used to specify the input data of the diagnostic object when the write operation is performing. The operational processors contain data generation units FTi and address generation units FAi that generate test impacts for several adjacent times of diagnostic. Transfer flags are formed because of comparing the codes of the current addresses in X and Y coordinates with NX, NY end address codes or GX, GY begin address codes. It does for implementing conditional transfer commands that provide access to all cells of the tested memory. When the read operation is performed, data from the selected memory cell is recorded in the registers of reaction Dout0, Dout1,…, Doutð-1. Synchronizing signals provides resolution of data recording. They are spaced apart from each other for the period of the access time to the diagnosed product. The read and reference data are compared by comparison schemes S0, S1, …, Sp-1, at the outputs of which the diagnostic result is generated. It can be masked by the code of the special register B. The project of a test diagnosis device has been developed in the Active-HDL. It consists of a microcontroller, an address counter of micro-operations, an address generation unit, a data generation unit, a data comparator, and a conditional transfer flags generation unit. The completed verification of the project confirmed its operability. In the proposed structure of test diagnosis device, the test generation frequency is determined only by the switching time and the output registers, and depends on the propagation time of the signals through the communication line. The proposed principle of constructing a test diagnosis device can be applied for designing of complexes for test diagnostic of digital systems containing built-in memory.
Keywords
	memory chip, test diagnostics, diagnostic test device
Library reference
	Evdokimov A.P., Ryabtsev V.G., Melikov A.V. Principles of Designing Devices for Test Diagnosing of High-speed Microchips and Semiconductor Memory // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 23-30. doi:10.31114/2078-7707-2018-2-23-30
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D004.pdf