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Analysis of Power Consumption of Matching Signals Summation Circuits for 65 nm CMOS Associative Memory Registers
Authors
	Antonyuk A.V.
	Stepanov P.V.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-2-109-114
Abstract
	Power consumptions of two registers of content-addressable memory (CAM) based on STG DICE memory cells were analyzed. Considered CAM registers have different summation schemes of matching signals – the scheme based on combinational logic (CL) and the scheme based on match line (ML). The elements of matching (CAM cells) and the elements of masking (mask cells) based on upset-hardened STG DICE memory cells are the same in register with CL and in register with ML, so they consume the same amount of power. CL scheme includes three 8-input NAND elements with compensation of single event effects, 5-input OR element and logical gates that provide logical masking of certain inputs. Inputs of CL scheme are connected to the outputs of elements of matching. Scheme with match line consists of PMOS precharge transistor, NMOS discharge transistor and match line ML that is connected to the supply through PMOS transistors that are controlled by elements of matching. In search operation, NMOS transistor opens try-ing to discharge ML. In case of match in all elements of matching, ML voltage become low. In case of miss in one or more elements, there is a short-through current in ML, and ML voltage remains high. Power consumption of CL scheme depends on number N of inputs of the scheme that change their logical states, because the number of switched logical gates inside CL depends on the N value. Analysis of the simulation results showed, that the value of power consumption of CL differs from 2 to 104 µW as a function of N value. Power consumption of ML depends on the matching result in register – match or miss. In case of miss, ML power depends on the value of short-through current that depends on number of mismatched bits. Value of ML power consumption differs from 48 to 57 µW and it practically equals the value of CL power consumption when a half of the CL inputs switches. So if in the step of CAM development, it is known that input data words of CAM differs from each other in average by less than a half of all bits, then CL is preferable to save power in CAM. Analysis of topology and simulation results showed, that ML takes 35% less area on the chip and has 22% less output bit of matching delay compared to CL.
Keywords
	combinational logic, content-addressable memory, design, logical element, power consumption, simulation, topology
Library reference
	Antonyuk A.V., Stepanov P.V. Analysis of Power Consumption of Matching Signals Summation Circuits for 65 nm CMOS Associative Memory Registers // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 109-114. doi:10.31114/2078-7707-2018-2-109-114
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D024.pdf