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Listing of works with the partition by the subject of reports. Click on the work title to see its details. The selected set may be restricted by specifying a range of conference years, or by selecting a specific topic.

Select: from 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 to 2005 2006 2008 2010 2012 2014 2016 2018 2020 2021 2022 2023 2024 year

All topics ADC design problems Cellular automata Design of System-on-chip (SoC) and IP-blocks Design of VLSI elements Design of VLSI signal processors Design of analog and mixed functional blocks of VLSI Design of digital functional blocks of VLSI Design of fault-tolerance systems Design of micro-electromechanical systems Design of nanoelectronic devices Design of nanoelectronic devices based on Josephson junctions Design of photodetecting VLSI Design of radiation-resistant VLSI Design of technological processes Designing components for aerospace and navigation technology Genetic algorithms in VLSI CAD Methods and algorithms for automated layout design Methods for high-level simulation Methods of device technology simulation of VLSI Methods of digital information processing and digital filters Methods of electro-thermal simulation Methods of logic synthesis and functional logic simulation ... Methods of simulation of VLSI electrical characteristics Models of devices for circuit simulation Neural networks Problems of development of sensory microcircuitry Simulation of data transfer channels Study of the magnetic properties of materials Unconventional computing systems Web-based VLSI CAD design of memory cells

Selection on topic: Design of fault-tolerance systems

Selected papers: from 2005 to 2024 year

In selection - 29 papers

A

C

D

F

H

I

M

O

P

R

S

T

3

A
	Algorithm for analysis of structures with triple modal reservation after failures Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory Analytical Method for Choosing the Most Efficient Algorithm for Fault-Tolerant Combinational Circuits Synthesis
C
	CMOS 65-nm static RAM on DICE cells with spacing groups of transistors Comparative analysis of fault-tolerant TMR-based integer operation blocks
D
	Design of the error-correcting code blocks using the two-phase CMOS logic elements Design principles for fault-tolerant random access memory for space applications Development of Concurrent Error Detection Circuit Based on Automated Generation of Error-Correcting Code Disadvantages of domestic analytical-experimental methods prediction of reliability of the integrated circuits
F
	Features of experimental research methods for memory with error correction
H
	Hardware and software solutions to increase the reliability of combinational logic in the FPGA basis without taking into account interconnections and the I/O blocks High-performance parallel BCH encoder with reconfigurable correction capability
I
	Implementation of Area Optimal FIR Filters Based on Lookup Tables for Sigma-Delta Modulator Signal Processing Implementation of an RNS Reverse Converter for General Moduli Sets Based on LUTs with Reference Points Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance Investigation of the corrective ability of modular codes used in AES systems
M
	Model for detecting counterfeit recovered SRAM based on accelerated aging
O
	On identifying trends in the problems of predicting the degradation of radio electronic systems under conditions of randomized observations Optimization methods of coding circuits based on the binary decision diagrams for synthesis of fault-tolerant micro- and nanoelectronic circuits
P
	Probabilistic methods for reliability evaluation of combinational circuits
R
	Reliability-Driven Logic Synthesis Using Arbitrary Standard Cell Library Reliability evaluation for SEU in cache in system-on-chip design
S
	Self-Dual Control of Combinational Circuits with Using Hamming Codes Simulating Integrated Circuit Immunity to Powerful Conducted Emissions in Circuits with Single Modal Reservation
T
	Ternary sum codes and their modifications The circuitry of electronic devices that operate in conditions of electromagnetic noise The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory The technique of logical circuit parameters selection in nanometer RHBD CMOS VLSI
3
	3 design recommendations for radiation-hardened high-density SRAM cells