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Solovyev R.A.

IPPM RAS

Listing of all the works of the author. Click on the work title to get the full information.

2005
		Solovyev R.A., Gavrilov S.V. Delay noise analysis, using graph of constraint pairs
2006
		Gavrilov S.V., Glebov A.L., Lyalinskaya O.V., Solovyev R.A. Application of standard cell characterization results in statistical timing analysis
		Solovyev R.A., Glebov A.L., Gavrilov S.V. Static timing analysis aware false conduct path detection in terms of logic implication
2008
		Solovyev R.A., Gavrilov S.V., Glebov A.L. Statistical timing analysis aware of reconvergence of conduction paths and transition variations
2010
		Gudkova O.N., Skachkova E.P., Muhanyuk N.N., Gavrilov S.V., Solovyev R.A. The Methods of Fast Characterization of Large Scale Integration Parameterized IP-blocks
2012
		Amerbaev V.M., Stempkovsky A.L., Solovyev R.A. Parallel computing in the ring of Gaussian integers over the Galois field GF(p)
2014
		Amerbaev V.M., Balaka E.S., Solovyev R.A., Telpukhov D.V. Analysis and synthesis of arithmetic unit of a field of Galois of prof. Pospelov D.A.
		Solovyev R.A., Balaka E.S., Telpukhov D.V. Device for calculation of vector dot product with error correction based on residue number system
		Telpukhov D.V., Amerbaev V.M., Balaka E.S., Solovyev R.A. Hardware implementation of FIR filter based on number-theoretic fast Fourier transform in residue number system
2016
		Telpukhov D.V., Solovyev R.A., Balaka E.S., Rukhlov V.S., Mikhmel A.S. Design features of the multipliers on the module using advanced CAD
		Stempkovsky A.L., Telpukhov D.V., Solovyev R.A., Telpukhova N.V. Probabilistic methods for reliability evaluation of combinational circuits
2018
		Solovyev R.A., Kustov A.G., Rukhlov V.S. The Technique for Implementing a Neural Network for Recognizing Handwritten Digits in FPGAs Based on Fixed Point Calculations
2020
		Rukhlov V.S., Solovyev R.A., Kustov A.G. Hardware and software solutions to increase the reliability of combinational logic in the FPGA basis without taking into account interconnections and the I/O blocks
2022
		Stempkovsky A.L., Telpukhov D.V., Mkrtchan I.A., Solovyev R.A. Implementation of an RNS Reverse Converter for General Moduli Sets Based on LUTs with Reference Points
		Kustov A.G., Solovyev R.A., Stempkovsky A.L., Telpukhov D.V. Hardware Implementation of a Neural Network for Object Detection in FPGA
		Zhigulin A.S., Solovyev R.A. Hardware Implementation of an Accelerated Approximated Matrix Multiplier Based on MADDNESS Algorithm