2006  
 
Bibilo P.N., Kochanov D.A. Optimizational transformations of VHDLmodels of digital systems

 
Bibilo P.N., Kardash S.N., Romanov V.I. SsVER  system of synthesis and verification of combinational logic schemes

2008  
 
Bibilo P.N., Audzeyeu M.A. Designing of regular circuits with consecutive connections of transistors

 
Kirienko N.A. The subsystem for processing structurefunctional descriptions of circuits in a CAD system

2010  
 
Romanov V.I., Bibilo P.N., Loginova I.P., Cheremisinova L.D. Computeraided design of topology of functional blocks of custom digital VLSI

 
Bibilo P.N. Decomposition of Boolean Functions for BDD

 
Cheremisinova L.D., Cheremisinov D.I. Low Power Driven Optimization of TwoLevel Logic Circuits

2012  
 
Audzeyeu M.A., Zaitsay V.S. Design criteria of Frequency selection for the internal oscillator UHF RFID tags

 
Bibilo P.N., Cheremisinova L.D., Kardash S.N., Kirienko N.A., Leonchik P.V., Novokov D.Ya., Romanov V.I., Cheremisinov D.I. LowPower Synthesis of Logical CMOS Circuits

 
Bibilo P.N., Soloviev A.L. VHDLSimulationBased Evaluation of CMOSCircuits Power Consumption

2014  
 
Bibilo P.N. Decomposition and Minimization of Binary Decision Diagrams for Systems of Specified Boolean Functions

 
Cheremisinov D.I. FPGA reverse engineering by modeldriven development

 
Cheremisinova L.D. Verification of Logical Descriptions of Combinational Circuits

2016  
 
Bibilo P.N. The use of VHDL models of partial Boolean functions for the design of digital circuits

 
Cheremisinov D.I., Cheremisinova L.D. Use of parallel computing in VLSI computeraided design

2018  
 
Audzeyeu M.A., Bibilo P.N. Algorithmic Design of Digital Operational Units with Low Power Consumption

 
Cheremisinov D.I., Cheremisinova L.D. Decompilation of Flat CMOS Circuits in SPICE Format

2020  
 
Bibilo P.N., Lankevich Y.Y. Experimental Research of Effectiveness of Programs for Minimizing BDD Representations of Boolean Function Systems in Synthesis of Combinatorial CMOS Circuits

 
Bibilo P.N., Romanov V.I. The system of logical optimization of functional structural descriptions of digital circuits based on productionframe knowledge representation model

 
Cheremisinov D.I., Cheremisinova L.D. Verification of digital devices with concurrency behavior

2021  
 
Bibilo P.N. Algebraic Decompositions of Cofactors in BDD Representations of a Systems of Incompletely Defined Boolean Functions

2022  
 
Bibilo P.N., Audzeyeu M.A., Kirienko N.A. Estimating of the Power Consumption of Combinational CMOS Circuits Based on Logic VHDL Simulation

 
Bibilo P.N. Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words

 
Kardash S.N. Ortogonalization of the DNF System of Boolean Function

 
Cheremisinov D.I., Cheremisinova L.D. Reverse Engineering of VLSI for Equipment Safety

 
Cheremisinova L.D. Testing Systems with Behavior Parallelism Based on a Reduced Reachability Graph

