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Zheleznikov D.A.

IPPM RAS

Listing of all the works of the author. Click on the work title to get the full information.

2016
		Zheleznikov D.A., Lyalinsky A.A. The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism
2018
		Gavrilov S.V., Zheleznikov D.A., Chochaev R., Khvatov V.M. Partitioning Algorithm Based on Simulated Annealing for Reconfigurable Systems-on-Chip
		Tiunov I.V., Lipatov I.A., Zheleznikov D.A. Development of Methods for Architecturally-oriented Resynthesis in the Computer-aided Design Flow for FPGAs
		Zheleznikov D.A., Zapletina M.A., Khvatov V.M. The Rip-up and Reroute Technique Research for Physical Synthesis in the Basis of Reconfigurable SoCs
2020
		Gavrilov S.V., Khvatov V.M., Zheleznikov D.A., Garbulina T.V. Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip
		Zhukov D.V., Zheleznikov D.A., Zapletina M.A. Application of SAT Approach to Switch Blocks Routing for Reconfigurable System-on-a-chip
		Zapletina M.A., Zheleznikov D.A., Gavrilov S.V. The Hierarchical Approach to Island Style Reconfigurable System-on-a-chip Routing
2021
		Kuzminova T.D., Khvatov V.M., Zheleznikov D.A. Formation of the reduced logical elements library for FPGA