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Federal Research Center “Computer Science and Control” of the RAS

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Listing of all the works of the organization. Click on the work title to get the full information.

2005
		Stepchenkov Yu.A., Petrukhin V.S., Diachenko Yu.G. Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array
2006
		Stepchenkov Yu.A., Diachenko Yu.G., Grinfeld F.I., Morozov N.V., Plekhanov L.P., Denisov A.N., Filimonenko O.P., Fomin Yu.P. A Library of Self-Timed Elements or ASIC-Technology
		Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov Yu.A., Rogdestvenskene A.V. ASIAN - Self-Timed Logic Circuits Analysis Subsystem
		Plekhanov L.P. CAD system for self-timed electronic circuits RONIS
		Petrukhin V.S., Stepchenkov Yu.A., Morozov N.V., Stepchenkov D.Yu. SATOK - System for Self-Timed Integrated Circuits Testing
2008
		Stepchenkov Yu.A., Diachenko Yu.G., Bobkov S.G. Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
		Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu. Quasi Self-Timed Computing Device: Practical Implementation
2010
		Rozhdestvenskij Yu.V., Morozov N.V., Rogdestvenskene A.V. ASPECT – a Subsystem of Event Analysis of Self-Timed Circuits
		Diachenko Yu.G., Stepchenkov D.Yu., Morozov N.V. Characterization of pseudodynamic elements
		Plekhanov L.P. Design of Self-Timed Circuits: a Functional Approach
		Volchek V.N., Stepchenkov Yu.A., Petrukhin V.S., Prokofyev A.A., Zelenov R.A. Digital Signal Processor With Non-Conventional Recurrent Data-Flow Architecture
		Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu. Self-Timed Computing Device for High-Reliable Applications
2012
		Shneider A.U., Petrukhin V.S., Stepchenkov Yu.A. Development Principles of Debugging Tools for Recurrent-Computing Device
		Volchek V.N., Zelenov R.A., Prokofyev A.A. Test automation tool for the computing unit of the recurrent operational level
		Plekhanov L.P. The Functional Method of the Analysis of Speed-Independent Circuits of Any Size
2014
		Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V. Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
		Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Surkov A.V. Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
		Sokolov I.A., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G. Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
		Stepchenkov D.Yu., Petrukhin V.S., Morozov N.V. System Debugging Tools for Recurrent Computing Device
2016
		Stepchenkov Yu.A., Diachenko Yu.G., Khilko D.V., Petrukhin V.S. Recurrent data-flow architecture: features and realization problems
		Khilko D.V., Stepchenkov Yu.A., Shikunov D.I., Shikunov Yu.I. Recurrent data-flow architecture: technical aspects of implementation and modeling results
		Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Stepanov B.A., Djachenko D.Yu., Rogdestvenskene A.V. Self-Timed Floating Point Multiply-Add Unit
2018
		Sokolov I.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Delay-Insensitive Floating Point Multiply-Add-Subtract Unit
		Khilko D.V., Stepchenkov Yu.A., Shikunov Yu.I., Orlov G.A. Development of Capsule Programming Means for Recurrent Data-flow Architecture
2020
		Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Hardening Self-Timed Circuit Indication against Soft Errors
		Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Self-Timed Multiplier Performance Improvement Technique
		Stepchenkov Yu.A., Khilko D.V., Shikunov Yu.I., Orlov G.A. Specialized tag transformer for recurrent signal processor
2021
		Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Khilko D.V., Stepchenkov D.Yu., Shikunov Yu.I. Hardware verification of the recurrent signal processor on FPGA
		Diachenko Yu.G., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Rogdestvenskene A.V. Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance
2022
		Khilko D.V. Block FIR filter implementation with a data-flow recurrent signal processor
		Plekhanov L.P. Library composition optimization for self-timed circuit synthesis