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Belyaev A.A.

Electronic VLSI Engineering & Embedded Systems (ELVEES) R&D Center of Microelectronics

Listing of all the works of the author. Click on the work title to get the full information.

2005 
  Belyaev A.A., Solokhina T.V., Glushkov A.V., Aleksandrov Yu.N., Petrichkovich Ya.Ya., Mironova Yu.V., Gerasimov Yu.M.
MCam-01 mixed signal multimedia processor
  Kozlova N.N., Solokhina T.V., Gribov Yu.I., Belyaev A.A.
Configurable IP-cores architecture analysys using criterion of implementation ability in “MULTICORE” platform IP-library
  Glushkov A.V., Belyaev A.A., Putrya F.M., Alekseev I.N., Mironova Yu.V.
“MULTICORE” platform IP-library of SoC peripherals
  Belyaev A.A.
Organization of instruction pipeline in ELcore-õxTM DSP-cores of “MULTICORE” IP-library
2006 
  Belyaev A.A.
Pipeline structure optimization according to performance criterion for DSP-core with Harvard architecture
2008 
  Belyaev A.A., Gribov Yu.I., Solokhina T.V.
Pipelining and parallelization: two approaches to rise computational performance
2010 
  Belyaev A.A.
Pipeline Depth Influence on DSP Performance
2012 
  Belyaev A.A.
Architectural features of VELCore-01 video processing core
2014 
  Frolov D.S., Pirogov P.P., Aleksandrov Yu.N., Gribov Yu.I., Belyaev A.A.
IP-Core "ACC_Cores" as part system-on-chip. Multifunctional hardware accelerator Fast Fourier Transform - FFT_RT_Core
  Belyaev A.A., Gavrilov V.S., Kuznetsov D.A., Petrichkovich Ya.Ya., Solokhina T.V., Frolov D.S., Funkner A.A.
Evolution in the area of multicore heterogeneous video data processing systems
  Belyaev A.A., Kolesnikova I.Y., Kuznetsov D.A.
Motion Estimation IP-core Implementation for H.264 Full HD Video Codec
2021 
  Zhezlov K.A., Belyaev A.A., Putrya F.M.
Implementation of Methodology of SoC Interconnects Automated Performance Analysis into the Verification Route
  Belyaev A.A., Belyaev I.A., Petrichkovich Ya.Ya., Poperechny P.S.
High-performance parallel BCH encoder with reconfigurable correction capability
  Belyaev A.A., Belyaev I.A., Petrichkovich Ya.Ya.
Parameterizable matrix multiplier of fixed-point binary numbers in direct and complementary code
2022 
  Belyaev A.A., Shchuchkin E.Yu.
DC-DC Converter Conducted Emission Level Estimation at Design Stage
 

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