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Listing of all the works of the author. Click on the work title to get the full information.
| 2006 | |
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Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov Yu.A., Rogdestvenskene A.V.
ASIAN - Self-Timed Logic Circuits Analysis Subsystem
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| 2008 | |
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Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu.
Quasi Self-Timed Computing Device: Practical Implementation
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| 2010 | |
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Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu.
Self-Timed Computing Device for High-Reliable Applications
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Rozhdestvenskij Yu.V., Morozov N.V., Rogdestvenskene A.V.
ASPECT – a Subsystem of Event Analysis of Self-Timed Circuits
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| 2014 | |
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Sokolov I.A., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
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Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Surkov A.V.
Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
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Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V.
Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
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| 2016 | |
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Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Stepanov B.A., Djachenko D.Yu., Rogdestvenskene A.V.
Self-Timed Floating Point Multiply-Add Unit
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| 2018 | |
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Sokolov I.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu.
Delay-Insensitive Floating Point Multiply-Add-Subtract Unit
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| 2020 | |
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Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu.
Hardening Self-Timed Circuit Indication against Soft Errors
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Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu.
Self-Timed Multiplier Performance Improvement Technique
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| 2021 | |
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Diachenko Yu.G., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Rogdestvenskene A.V.
Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance
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